Feedback latch and method therefor
AssigneeMotorola, Inc.
InventorsClaude Moughanni, Jeffrey E. Maguire
Life of this patent
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Abstract
A latch (40) has a clocked feedback path (46) which performs a static latching function while using less power. The latch includes a feedback device (46) which is selectively decoupled from a feed-forward portion (42, 44) of the latch. In a normal mode of operation when the latch will be clocked often, the feedback device of the latch is not enabled and the latch effectively functions as a dynamic latch. When the latch becomes inactive for an extended period of time, the feedback device is again enabled and the latch is able to store a data value indefinitely.
Claims15
A latch comprising:
- a generation circuit having a first input terminal for receiving a periodic clock signal, a second input terminal for receiving a low power signal, and an output terminal for providing a gated clock signal, said generation circuit providing said periodic clock signal to said output terminal thereof if said low power signal is in a first logic state, said generation circuit providing said gated clock signal at a predetermined logic state if said low power signal is in a second logic state;
- a first gated inverter having a data input terminal for receiving an input signal of the latch, a control input terminal coupled to said output terminal of said generation circuit, and an output terminal;
- a second inverter having an input terminal coupled to said output terminal of said first gated inverter, and an output terminal for providing an output signal of the latch;
- and
- a third gated inverter having a data input terminal coupled to said output terminal of said second inverter, a control input terminal for receiving said low power signal, and an output terminal coupled to said input terminal of said second inverter, wherein when said low power signal is in said first logic state, said third gated inverter provides an output signal to said output terminal thereof to be a complement of an input signal at said data input terminal thereof, and when said low power signal is in said second logic state, said third gated inverter provides said output signal in a high impedance state;
- wherein when said low power signal is in said first logic state, said latch functions as a dynamic latch, and when said low power signal is in said second logic state, said latch functions as a static latch.
In a latch comprising a first gated inverter having a data input terminal for receiving an input signal, a control input terminal, and an output terminal, a second inverter having an input terminal coupled to said output terminal of said first gated inverter, and an output terminal for providing an output signal of the latch, and a third gated inverter having a data input terminal coupled to said output terminal of said second inverter, a control input terminal, and an output terminal coupled to said input terminal of said second inverter, the improvement wherein the latch further comprises:
- a generation circuit having a first input terminal for receiving a periodic clock signal, a second input terminal for receiving a low power signal, and an output terminal, coupled to said control input terminal of said first gated inverter, for providing a gated clock signal, said generation circuit providing said periodic clock signal to said output terminal thereof if said low power signal is in a first logic state, said generation circuit providing said gated clock signal at a predetermined logic state if said low power signal is in a second logic state;
- and
- wherein said third gated inverter further receives said low power signal at said control input terminal thereof, wherein when said low power signal is in said first logic state, said third gated inverter provides an output signal to said output terminal thereof to be a complement of an input signal at said data input terminal thereof, and when said low power signal is in said second logic state, said third gated inverter provides said output signal in a high impedance state.
A method for operating a latch, the latch comprising a first gated inverter having an input terminal for receiving an input signal of the latch and an output terminal, a second inverter having an input terminal coupled to the output terminal of the first gated inverter, and an output terminal for providing an output of the latch, and a third gated inverter having a data input terminal coupled to the output terminal of the second inverter, and an output terminal coupled to the input terminal of the second inverter, comprising the steps of:
- clocking the first gated inverter with a periodic clock input signal in a normal operation mode;
- disabling the third gated inverter in said normal operation mode;
- disabling the first gated inverter in a low power mode;
- and
- enabling the third gated inverter in response to entering said low power mode,
- wherein the latch functions as a dynamic latch using the first gated inverter and the second inverter in the normal operation mode, and as a static latch using the second inverter and the third gated inverter in the low power mode.
Dependencies are inferred from the claim text.