Semiconductor memory device
AssigneeOki Electric Industry Co., Ltd.
InventorNoboru Egawa
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.
Claims7
A semiconductor memory device comprising:
- a first input buffer that outputs a CMOS level signal in response to a first TTL level input signal, said first input buffer having a first transistor of a first conductivity, the first transistor having a gate to which the first TTL level input signal is input;
- and
- a second input buffer that responds to a second TTL level input signal and the CMOS level signal, said second input buffer having a second transistor of the first conductivity, the second transistor having a gate to which the second TTL level input signal is input;
- wherein a gate length of the second transistor is greater than a gate length of the first transistor.
Dependencies are inferred from the claim text.