Ram-logic tile for field programmable gate arrays
AssigneeCrosspoint Solutions, Inc.
InventorMichael G. Ahrens
Life of this patent
Estimating the term…
Abstract
An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.
Claims23
In a field programmable gate array having a plurality of conducting lines in a first direction and a plurality of conducting lines in a second direction perpendicular to said first direction;
- an array of circuit blocks located at the intersections of said first and second direction conducting lines and connected to said conducting lines;
- and a plurality of wiring segments programably connecting said circuit blocks;
- a circuit block comprising:
- a plurality of input terminals, at least one input terminal coupled to a wiring segment and at least one input terminal coupled to a first direction conducting line;
- a bidirectional terminal coupled to a second direction conducting line;
- an output terminal coupled to a wiring segment;
- a multiplexer having first and second inputs, a control input and an output;
- said first input, said second input and said control input being coupled to an input terminal of said at least one input terminal coupled to a wiring segment;
- and said output coupled to said output terminal through a first node;
- a first transmission gate, responsive to an input terminal of said at least one input terminals coupled to a first direction conducting line, coupled to said bidirectional terminal and to said first node;
- and
- a tri-state output, responsive to an input terminal of said at least one input terminal coupled to a first direction conducting line, having an input and an output, said input coupled to said first node and said output coupled to said bidirectional terminal.
In a field programmable gate array, a circuit block comprising:
- a multiplexer having first and second inputs, a control input and an output;
- a first transmission gate, responsive to a first conducting line, coupled to a second conducting line and to said multiplexer output;
- and
- a tri-state output, responsive to a third conducting line, having an input and an output, said input coupled to said multiplexer output and said output coupled to said second conducting line.
In a field programmable gate array, a circuit block comprising:
- a first transmission gate, responsive to a first conducting line, coupled in parallel to a second conducting line;
- a tri-state output, responsive to a third conducting line, having an input and an output, said input coupled to said first transmission gate and said output coupled to said second conducting line;
- and
- a multiplexer having first and second inputs, a control input and an output, said output being coupled to said first transmission gate.
In a field programmable gate array, a circuit block comprising:
- a first transmission gate, responsive to a first conducting line, coupled in parallel to a second conducting line, wherein said first transmission gate is further responsive to a third conducting line;
- a multiplexer having first and second inputs, a control input and an output, said output being coupled to said first transmission gate;
- and
- a NAND gate having as input said first and third conducting lines and output controllably coupled to said first transmission gate.
In a field programmable gate array, a circuit block comprising:
- a first transmission gate, responsive to a first conducting line, coupled in parallel to a second conducting line;
- a multiplexer having first and second inputs, a control input and an output, said output being coupled to said first transmission gate;
- and
- a second transmission gate, responsive to a third conducting line, coupled between said first transmission gate and said multiplexer output.
Dependencies are inferred from the claim text.