Semiconductor wafer contact system and method for contacting a semiconductor wafer

A semiconductor wafer contact test system comprising:

• a base including a grid of raised supports;
• a compliant layer overlying the grid of raised supports;
• and
• a removable flexible circuit layer overlying the compliant layer, the removable flexible circuit layer including a grid of electrical contacts, each of the grid of electrical contacts aligned to a different one of the grid of raised supports.

A semiconductor wafer contact test system comprising:

• a base including a grid of raised supports wherein the base includes a vacuum orifice;
• a compliant layer overlying the grid of raised supports;
• and
• a removable flexible circuit layer overlying the compliant layer, the removable flexible circuit layer including a grid of electrical contacts, each of the grid of raised supports aligned to a different one of the grid of electrical contacts.

A method of manufacturing a semiconductor device comprising:

• providing a base including a grid of raised supports;
• covering the grid of raised supports with a compliant layer;
• providing a removable flexible circuit layer overlying the compliant layer, the removable flexible circuit layer including a grid of electrical contacts, each of the grid of electrical contacts aligned to a different one of the grid of raised supports;
• and
• pressing the grid of raised supports towards the grid of electrical contacts.

A method of contacting a semiconductor wafer, the method comprising the steps of:

• providing a base substrate including a first array of ridges separated from one another by respective recessed regions;
• providing a circuit layer overlying the base substrate, the circuit layer comprising a second array of electrical contacts, each of the first array of ridges aligned to only one of the second array of electrical contacts;
• and
• pressing the first array of ridges against the second array of electrical contacts, the respective recessed regions permitting a plurality of portions of the circuit layer to bow.