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AssigneeSGS-Thomson Microelectronics S.A.
InventorsGiorgio Pedrazzini, Giuseppe Scrocchi, Paolo Cordini, Domenico Rossi
Estimating the term…
A fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance. The first comparator exerts an open-loop current mode control. The second comparator, establishing a second higher current threshold than the current threshold set by the first comparator, triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator. The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.
A method for driving a power output terminal, comprising the steps of:
A digital, current mode, PWM control circuit for an output stage comprising a sensing resistance of an input current connected in series with a power switch of the output stage, a bistable driving circuit having a clock input suitable to receive a PWM clock signal and a reset input driven by an output of a multi-input logic circuit, comprising:
A switched power output subsystem, comprising:
A switched power output subsystem, comprising:
Dependencies are inferred from the claim text.