Bidirectional thyristor with MOS turn-on and turn-off capability

A MOS gate controlled bidirectional thyristor, comprising:

• a wafer of semiconductor material having first and second spaced, parallel planar surfaces, at least a portion of the thickness of said wafer which extends from said first planar surface comprising a relatively lightly doped substrate of a first conductivity type for receiving junctions, at least a portion of the thickness of said wafer which extends from said second surface comprising a base region of a second conductivity type which is opposite to said first conductivity type;
• at least one well region of said second conductivity type formed in said relatively lightly doped substrate and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface;
• at least one body region of said first conductivity type formed in said well region and extending from said first semiconductor surface to a second depth beneath said semiconductor surface which is shallower than said first depth, said body region being radially inwardly spaced along said first semiconductor surface from said well region thereby to define a first channel region along said first semiconductor surface between said body region and said relatively lightly doped substrate;
• at least one source region of said second conductivity type formed in said body region and extending from said first semiconductor surface to a third depth beneath said semiconductor surface which is shallower than said second depth, said source region being radially inwardly spaced along said first semiconductor surface from said well region thereby to define a second channel region along said first semiconductor surface between said source region and said well region;
• first electrode means disposed on said first semiconductor surface and connected to said body region and said source region;
• gate insulation layer means on said first surface disposed at least on said channel regions;
• gate electrode means on said gate insulation layer means and overlying said channel regions;
• at least one relatively highly doped region of said first conductivity type formed in said base region of second conductivity type and extending from said second semiconductor surface;
• and
• second electrode means disposed on said second semiconductor surface and connected to said relatively highly doped region of said first conductivity type, to said base region, and to said relatively lightly doped substrate of said first conductivity type.