Apparatus for and method of providing long integration times in an IR detector

A device comprising:

• first means, including a quantum well infrared photoconducting detector arranged to receive a photon flux, for generating a current signal having a magnitude indicative of an intensity of said photon flux;
• a first capacitive structure which is charged by said current signal;
• a second capacitive structure;
• a first transistor switch having a first conduction interval, said first transistor switch being arranged between said first capacitive structure and said second capacitive structure to transfer a charge accumulated by said first capacitive structure to said second capacitive structure;
• a third capacitive structure;
• and
• a second transistor switch having a second conduction interval having no substantial overlap with said first conduction interval, said second transistor switch being arranged between said second capacitive structure and said third capacitive structure to transfer a charge accumulated by said second capacitive structure to said third capacitive structure.

A device comprising:

• first means, including a quantum well infrared photoconducting detector arranged to receive a photon flux, for generating a current signal having a magnitude indicative of an intensity of said photon flux, said first means also including buffering means connected to said quantum well infrared photoconducting detector for maintaining a substantially constant voltage across said quantum well infrared photoconducting detector;
• a first charge well transistor having a gate connected to said buffering means, said gate forming a first capacitive structure which is charged by said current signal;
• a second charge well transistor;
• a first transistor switch having a first conduction interval, said first transistor switch being arranged between said gate of said first charge well transistor and a gate of said second charge well transistor to transfer a charge accumulated by said first capacitive structure to a second capacitive structure formed by said second charge well transistor;
• a third charge well transistor;
• and
• a second transistor switch having a second conduction interval having no substantial overlap with said first conduction interval, said second transistor switch being arranged between said gate of said second charge well transistor and a gate of said third charge well transistor to transfer a charge accumulated by said second capacitive structure to a third capacitive structure formed by said third charge well transistor.