US 5,629,240 A · Method for direct attachment of an on-chip bypass capacitor in an integrated circuit

Abstract

Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or solder. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

Claims20

Dependent claims

In an integrated circuit that includes a V.sub.DD peripheral pad and a first conductive trace coupled thereto, and a V.sub.SS peripheral pad and a second conductive trace coupled thereto a retrofittable method of directly attaching a capacitor on said integrated circuit to bypass noise between a trace carrying V.sub.SS and a trace carrying V.sub.DD, the method comprising the following steps:

(a) forming in said integrated circuit a first column-shaped opening and a second column-shaped opening spaced-apart a distance .DELTA.X from each other, wherein said .DELTA.X approximates a lateral distance separating first and second connecting pads on said capacitor;
said first column-shaped opening extending from an upper surface of said integrated circuit downward to at least expose an upper surface region of said first conductive trace, and said second opening extending from an upper surface of said integrated circuit downward to at least expose an upper surface region of said second conductive trace;
(b) converting the first and second column-shaped openings into first and second columnar electrically conductive elements;
and
(c) mounting said capacitor on said upper surface directly over said integrated circuit such that said first and second connecting pads on said capacitor directly overlie respective uppermost regions of said first and second columnar electrically conductive elements, and electrically coupling said first and second connecting pads respectively to said first and second columnar electrically conductive elements.

2 more elements

For use with a fabricated integrated circuit including a V.sub.DD pad and a first conductive trace coupled thereto, and a V.sub.SS pad and a second trace coupled thereto, a retrofittable method of mounting a capacitor on said integrated circuit to bypass noise between traces carrying V.sub.SS and V.sub.DD, the method comprising the following steps:

(a) identifying a first region of said first conductive trace and a second region of said second conductive trace underlying a portion of said integrated circuit whereat first and second connecting pads of said capacitor are to be located, said first region and said second region being spaced-apart from each other laterally a distance .DELTA.X corresponding to a lateral distance separating said first and second connecting pads;
(b) forming a first column-shaped opening and a second column-shaped opening spaced-apart said distance .DELTA.X from said first column-shaped opening;
said first column-shaped opening extending from an upper surface of said integrated circuit downward to at least expose an upper surface of said first region of said first conductive trace, and said second opening extending from an upper surface of said integrated circuit downward to at least expose an upper surface of said second region of said second conductive trace;
(c) converting the first and second column-shaped openings into first and second columnar electrically conductive elements;
and
(d) mounting said capacitor on said upper surface directly over said integrated circuit such that said first and second connecting pads on said capacitor directly overlie respective uppermost regions of said first and second columnar electrically conductive elements, and electrically coupling said first and second connecting pads to an uppermost region of said first and second columnar electrically conductive elements.

3 more elements

Dependencies are inferred from the claim text.

Method for direct attachment of an on-chip bypass capacitor in an integrated circuit

Life of this patent

Method for direct attachment of an on-chip bypass capacitor in an integrated circuit

Life of this patent

Abstract

Claims20