US 5,629,215 AGranted

Method of fabricating and contacting ultra-small three terminal semiconductor devices

AssigneeMotorola, Inc.

InventorsHerbert Goronkin, Martin Walther, Raymond K. Tsui

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Abstract

Ultra-small three terminal semiconductor devices and a method of fabrication including patterning the planar surface of a substrate and a control layer to form a first and second pattern edge and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edges so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.

Claims8

Dependent claims

A method of fabricating three terminal semiconductor devices comprising the steps of:

providing a supporting substrate having a planar surface;
forming a control layer on the planar surface of the supporting substrate, the control layer having a planar surface opposite the supporting substrate;
patterning the planar surface of the control layer at least down to the planar surface of the substrate to form a first pattern edge with a side wall;
conformably forming a layer of material over the planar surface of the control layer and the planar surface of the supporting substrate, including the side wall of the first pattern edge;
anisotropically removing the layer of material so as to leave a selected thickness of the layer of material covering the side wall;
etching the planar surface of the supporting substrate to form a second pattern edge laterally spaced the selected thickness from the first pattern edge by using the selected thickness of the layer of material covering the side wall as a mask;
removing the selected thickness of the layer of material covering the side wall;
and
consecutively forming a plurality of overlying layers of material, at least partially defining a semiconductor device, in overlying relationship to first and second opposite sides of each of the first and second pattern edges so that discontinuities are produced in the layers at each of the first and second pattern edges and a first layer of the plurality of layers on the first opposite side of the first pattern edge is aligned with and in electrical contact with a second layer of the plurality of layers on the second opposite side of the first pattern edge, a third layer of the plurality of layers on the second opposite side of the first pattern edge is aligned with and in electrical contact with the control layer, and a fourth layer of the plurality of layers on the first opposite side of the second pattern edge is aligned with and in electrical contact with a fifth layer of the plurality of layers on the second opposite side of the second pattern edge.

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Dependencies are inferred from the claim text.

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Abstract

A method of fabricating three terminal semiconductor devices comprising the steps of:

providing a supporting substrate having a planar surface;
forming a control layer on the planar surface of the supporting substrate, the control layer having a planar surface opposite the supporting substrate;
patterning the planar surface of the control layer at least down to the planar surface of the substrate to form a first pattern edge with a side wall;
conformably forming a layer of material over the planar surface of the control layer and the planar surface of the supporting substrate, including the side wall of the first pattern edge;
anisotropically removing the layer of material so as to leave a selected thickness of the layer of material covering the side wall;
etching the planar surface of the supporting substrate to form a second pattern edge laterally spaced the selected thickness from the first pattern edge by using the selected thickness of the layer of material covering the side wall as a mask;
removing the selected thickness of the layer of material covering the side wall;
and
consecutively forming a plurality of overlying layers of material, at least partially defining a semiconductor device, in overlying relationship to first and second opposite sides of each of the first and second pattern edges so that discontinuities are produced in the layers at each of the first and second pattern edges and a first layer of the plurality of layers on the first opposite side of the first pattern edge is aligned with and in electrical contact with a second layer of the plurality of layers on the second opposite side of the first pattern edge, a third layer of the plurality of layers on the second opposite side of the first pattern edge is aligned with and in electrical contact with the control layer, and a fourth layer of the plurality of layers on the first opposite side of the second pattern edge is aligned with and in electrical contact with a fifth layer of the plurality of layers on the second opposite side of the second pattern edge.

6 more elements