US 5,627,842 A · Architecture for system-wide standardized intra-module and inter-module fault testing

Abstract

Apparatus and method for hierarchical, centralized boundary-scan fault-testing of extended electronic circuits, including inter-board testing, within a unified, standard protocol. During this testing, each board is "viewable" from the central test control in the same way that it is viewable when standing alone, before being incorporated into an extended system. The preferred embodiment of the invention is based on IEEE Std 1149.1, and is to be used with integrated circuits compliant with that standard. Because of this, the IEEE Std 1149.1 test elements--including but not limited to extensive micro-code--prepared for the testing of the board individually can be incorporated into the system-wide testing. The invention makes use of a "parking" of integrated circuit test rings with any desired test vector in their boundary scan registers, so that they can subsequently be viewed from another board as part of inter-board fault testing. In its preferred embodiment the invention provides for the parallel coupling of all backplane slots to the standard test bus implicit in IEEE Std 1149.1. The coupling of test rings to the system test bus is through a SLOT Link apparatus that incorporates a Selection Controller (a three-state finite state machine in the preferred embodiment) for enabling one board to be selected for testing. an address facility ensuring that only one slot is selected at a time. Also included in the preferred embodiment test architecture on each board is a switching network and one or more Local Serial Port (LSP) Ring Controllers which, in the preferred embodiment, are four-state finite state machines. In this way a plurality of test rings on a single board can be flexibly configured for testing, so that a single test ring or several of the test rings in series are tested. These LSP Ring Controllers are also used to "park" the Test Rings for subsequent inter-board testing.

Claims25

Dependent claims

Boundary-scan test apparatus for use with an electronic system having a printed circuit board, said printed circuit board having one or more test chains of boundary-scan-testable integrated circuits (ICs), wherein said printed circuit board is removably insertable into a circuit board slot, said test apparatus comprising:

(a) a backplane test bus connectable to a central test controller and connected to said circuit board slot;
and
(b) a test chain controller for activating a particular one of said test chains so that a boundary-scan test vector can be transferred to said particular test chain and for then parking said particular chain with said test vector remaining in said chain, wherein said test chain controller is connected to said backplane test bus whenever said board is inserted into said circuit board slot.

A boundary-scan test apparatus for use with an electronic system having a plurality of printed circuit boards, each of said plurality of printed circuit boards having one or more test chains of boundary-scan-testable integrated circuits (ICs), wherein each of said printed circuit boards is removably insertable into any one of a plurality of circuit board slots, said test apparatus comprising:

(a) a backplane test bus connectable to a central test controller, wherein said backplane test bus is connected in parallel to each of said plurality of circuit board slots:
(b) a board selection device for selecting any one of said plurality of printed circuit boards, wherein said board selection device is connected to said backplane test bus;
(c) a plurality of test chain controllers corresponding in number to the number of test chains on an individual printed circuit board, said test chain controllers designed to activate a particular test chain of said test chains so that a boundary-scan test vector can be transferred to said particular test chain and for then parking said particular test chain with said test vector remaining in said test chain;
and
(d) board identification means for establishing particular board identifiers corresponding to said plurality of printed circuit boards, wherein said board identification means is connectable to said board selection device.

2 more elements

Apparatus for testing an electronic system containing one or more circuit modules, each module having one or more IEEE-Std-1 149.1-compliant integrated circuits (ICs) coupled together by local test buses into local test rings, said apparatus comprising:

a. a system test bus connectable to a central test controller and connected in parallel with circuit module slots into which said circuit modules are insertable,
b. a module interface circuit associated with each said module, said module interface circuit comprising a SLOT Link Controller, a SLOT Link Instruction Register, SLOT Link Data Registers, Selection Controller logic means and Ring Controller logic means,
c. a distinct identification means (SLOT-ID) associated with each of said circuit module slots, wherein said Selection Controller logic means permit each said module to be selected for testing by said central test controller by means of transmitting a specific identifier signal on said system test bus, wherein said Selection Controller logic means:
i. is placeable in a Wait state receptive to said identifier signal and designed to compare said identifier signal with said SLOT-ID and
ii. which then changes to a Selected state if and only if said identifier signal matches said SLOT-ID and which changes into an UnSelected state otherwise,
wherein said Selection Controller logic means in said Selected state enables coupling between said system test bus and a local test ring of said module subject to further regulation by said Ring Controller logic means such that said ICs on said local test ring are then testable by said central test controller using IEEE Std 1 149.1 test protocol, and wherein said Selection Controller logic means is returnable by said central test controller to said Wait state in such a manner that said ICs on said local test ring are left in a test state imposed by said central test controller during prior testing.

3 more elements

A boundary-scan test method for testing an electronic system having a printed circuit board, said printed circuit board having one or more test chains of boundary-scan-testable integrated circuits (ICs), wherein said printed circuit board is removably insertable into a circuit board slot connected to a backplane test bus, said test method comprising the steps of:

(a) activating a particular first one of said test chains;
(b) conveying a first boundary-scan input test vector from a central test controller to said first particular test chain;
(c) parking said first particular chain with said first input test vector remaining in said first particular chain;
(d) activating a particular second one of said test chains;
and
(e) retrieving a second boundary-scan output test vector from said second particular test chain.

3 more elements

A boundary-scan test method for testing an electronic system having a plurality of printed circuit boards, each of said plurality of printed circuit boards having one or more test chains of boundary-scan-testable integrated circuits (ICs), wherein each of said printed circuit boards is removably insertable into any one of a plurality of circuit board slots connected to a backplane test bus, said test method comprising the steps of:

(a) establishing particular board identifiers for each of said plurality of printed circuit boards;
(b) selecting any one of said plurality of printed circuit boards using a board selection device, said board selection device comprising a plurality of individual board selectors corresponding in number to that of said printed circuit boards;
(c) transferring a first boundary-scan input test vector from a central test controller to a first particular test chain of a selected printed circuit board;
(d) parking said first particular chain with said first input test vector remaining in said first particular chain;
and
(e) transferring a first output test vector out from a second particular test chain.

3 more elements

Dependencies are inferred from the claim text.

Architecture for system-wide standardized intra-module and inter-module fault testing

Life of this patent

Architecture for system-wide standardized intra-module and inter-module fault testing

Life of this patent

Abstract

Claims25