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US 5,627,624 AGranted
Integrated circuit test reticle and alignment mark optimization method
AssigneeLSI Logic Corporation
InventorsRandy Yim, Christopher Neville
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AssigneeLSI Logic Corporation
InventorsRandy Yim, Christopher Neville
Estimating the term…
A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.
A method of fabricating a semiconductor integrated circuit including a plurality of overlying process layers, comprising the steps of:
A semiconductor integrated circuit including a plurality of overlying process layers, fabricated by a method comprising the steps of:
An archive wafer fabricated by a method comprising the steps of:
Dependencies are inferred from the claim text.