US 5,627,598 AGranted

Display apparatus including aspect ratio converter and child picture processing with four field sequence memory

AssigneeSony Corporation

InventorSusumu Tsuchida

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Abstract

A display apparatus wherein a video signal of a child picture read out at a double speed is inserted accurately with a high resolution into a parent picture of another video signal having a double frequency. Control signals for designating a write area and a read-out area of a four field sequence memory provided for forming a double speed field frequency is formed in accordance with odd/even number field discrimination signals for write and read-out video signals, a vertical synchronizing signal prior to double speed conversion and a double speed synchronizing signal for a parent picture so that, even when the parent picture is scrolled, passing of the read-out side memory area does not take place. Where the parent picture is formed from a video signal of the interlace system by a line double speed, the double speed child picture video signal is delayed, upon reading out in an even-numbered field, by one horizontal scanning period so that lines may be overlapped between the parent and child pictures.

Claims14

Dependent claims

A video display apparatus, comprising:

frequency conversion means for converting a first video signal of a parent picture into a second video signal of a double speed field frequency;
aspect ratio conversion means for converting an aspect ratio of the second video signal whose field frequency has been converted by said frequency conversion means and producing a third video signal having a predetermined aspect ratio;
child picture processing means including a four field sequence memory for converting a fourth video signal of a child picture into a fifth video signal of the double speed field frequency;
display means for inserting the fifth video signal output from said child picture processing means into the third video signal output from said aspect ratio conversion means and for displaying a combined video signal on a scanning screen, said display means including a deflection system for generating a double-speed vertical synchronizing signal and a double-speed horizontal synchronizing signal by using at least the fifth video signal converted from the fourth video signal of the child picture and for controlling a scanning of the Scanning screen;
thinning out means for thinning out a double speed synchronizing signal for scanning said display means by using a window signal of a predetermined width centered at a vertical synchronization position prior to conversion to the double speed;
and
a control circuit for forming an area control signal for said four field sequence memory of said child picture processing means by using a thinned out vertical synchronization pulse signal output from said thinning out means and the double-speed vertical synchronizing and horizontal synchronizing signals from said deflection system, for reading out said four field sequence memory twice for each field in accordance with the area control signal, and for controlling write and read-out areas of said four field sequence memory in accordance with the area control signal so as to display the child picture free from read/write address passing in said four field sequency memory.

4 more elements

A display apparatus, comprising:

line frequency conversion means for converting a first video signal of a parent picture for one horizontal period into a second video signal of a double speed line frequency;
aspect ratio conversion means for converting an aspect ratio of the second video signal whose line speed has been doubled by said line frequency conversion means and producing a third video signal having a predetermined aspect ratio;
child picture processing means including a memory for converting a fourth video signal of a child picture into a fifth video signal of the double speed line frequency in units of a field;
display means for inserting the fifth video signal output from said child picture processing means into the third video signal of the double speed line frequency output from said aspect ratio conversion means and for displaying a combined video signal on a scanning screen, said display means including a deflection system for generating a double-speed vertical synchronizing signal and a double-speed horizontal synchronizing signal by using at least the fifth video signal converted from the fourth video signal of the child picture and for controlling a scanning of the scanning screen;
and
a control circuit for discriminating a field of the video signal read out by said child picture processing means using a synchronizing signal prior to the double speed conversion and delaying outputting of the picture displaying timing for an even-numbered field for one horizontal period and for reading out said memory twice for each field in response to the double speed vertical synchronizing and horizontal synchronizing signals from said deflection system.

3 more elements

A video signal processing circuit for a display apparatus, comprising:

frequency conversion means for converting a first video signal of a parent picture into a second video signal of a double speed field frequency;
aspect ratio conversion means for converting an aspect ratio of the second video signal whose field frequency has been converted by said frequency conversion means and producing a third video signal having a predetermined aspect ratio;
child picture processing means including a four field sequence memory for converting a fourth video signal of a child picture into a fifth video signal of the double speed field frequency;
display means for inserting the fifth video signal output from said child picture processing means into the third video signal output from said aspect ratio conversion means and for displaying a combined video signal on a scanning screen, said display means including a deflection system for generating a double-speed vertical synchronizing signal and a double-speed horizontal synchronizing signal by using at least the fifth video signal converted from the fourth video signal of the child picture and for controlling a scanning of the scanning screen;
thinning out means for thinning out a double speed synchronizing signal for scanning said display means by using a window signal of a predetermined width centered at a vertical synchronization position prior to conversion to the double speed;
and
a control circuit for forming an area control signal for said four field sequence memory of said child picture processing means by using a thinned out vertical synchronization pulse signal output from said thinning out means and the double-speed vertical synchronizing and horizontal synchronizing signals from said deflection system, for reading out said four field sequence memory twice for each field in accordance with the area control signal, and for controlling write and read-out areas of said four field sequence memory in accordance with the area control signal so as to display the child picture free from read/write address passing in said four field sequency memory.

4 more elements

A video signal processing circuit for a display apparatus, comprising:

line frequency conversion means for converting a first video signal of a parent picture for one horizontal period into a second video signal of a double speed line frequency;
aspect ratio conversion means for converting an aspect ratio of the second video signal whose line speed has been doubled by said line frequency conversion means and producing a third video signal having a predetermined aspect ratio;
child picture processing means including a memory for converting a fourth video signal of a child picture into a fifth video signal of the double speed line frequency in units of a field;
display means for inserting the fifth video signal output from said child picture processing means into the third video signal of the double speed line frequency output from said aspect ratio conversion means and for displaying a combined video signal on a scanning screen, said display means including a deflection system for generating a double-speed vertical synchronizing signal and a double-speed horizontal synchronizing signal by using at least the fifth video signal conversed from the fourth video signal of the child picture and for controlling a scanning of the scanning screen;
and
a control circuit for discriminating a field of the video signal read out by said child picture processing means using a synchronizing signal prior to the double speed conversion and delaying outputting of the picture displaying timing for an even-numbered field for one horizontal period and for reading out said memory twice for each field in response to the double speed vertical synchronizing and horizontal synchronizing signals from said deflection system.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/546,286Filed 20 Oct 1995 · continuation
Priority: JP 5-09382730 Mar 1993
Granted: 6 May 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H04N 7/0132
By changing the field or frame frequency of the incoming video signal, e.g. frame rate converter: the field or frame frequency of the incoming…
H04N 5/45
For displaying additional information: picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
H04N 7/012
Involving conversion of the spatial resolution of the incoming video signal: conversion between an interlaced and a progressive signal
H04N 9/641
Circuits for processing colour signals: multi-purpose receivers, e.g. for auxiliary information