Video synchronization circuit comprising a PLL with a circuit to set the frequency of the output signal when the feedback signal is not present

A video system pulse generating circuit for generating a video system pulse for driving an image processing system, the video system pulse having a frequency of an integral multiple of a frequency of an input video synchronizing signal and being synchronized with the video synchronizing signal, comprising:

• (a) a phase locked loop circuit for receiving the video synchronizing signal and an output signal of the circuit for generating the video system pulse, and for synchronizing phases of the video synchronizing signal and of the output signal of the circuit for generating the video system pulse;
• (b) a dividing circuit for reducing a frequency of an output of the phase locked loop circuit to 1/N (wherein N is an integer);
• and
• (c) a synchronizing range determining circuit connected to the phase locked loop circuit in order to set a frequency of an output signal to an expected value of the video system pulse instead of the frequency of the video system pulse which is fed back and input into the phase locked loop circuit,
• wherein, upon start of synchronizing operation in the synchronizing range determining circuit, when the video system pulse is not generated, a signal to be input into the phase locked loop circuit instead of the video system pulse is a pulse from the synchronizing range determining circuit.