Display buffer using minimum number of VRAMs

Display buffer circuitry comprising:

• a display buffer comprising a plurality of banks of random access memory devices, each said bank of random access memory device having a plurality of ordered rows of data storage locations including a first row and a last row, said storage locations of each row ordered and including a first data storage location and a last data storage location;
• circuitry for controlling the storage of a plurality of sequenced lines of display data in said display buffer, each said sequenced line of display data comprising a plurality of sequenced data words each defining a pixel, said circuitry for controlling operable to:
• store sequenced lines of display data in contiguous locations in a first one of said banks of random access memory devices, a first word of a first one of said sequenced lines of display data being stored in a location offset from said first data storage location of said first row of said first bank of random access memory devices such that a last word of a last line of display data being stored in said first bank of random access memory devices is stored in said last data storage location of said last row of said first bank of random access memory devices;
• store a next line of said sequenced lines of display data in said first row of a second one of said banks of random access memory devices, a first word of said next line of display data being stored in said first data storage location of said first row of said second bank of random access memory devices;
• store a last one of said sequenced lines of display data being stored in said second bank of random access memory devices such that a last word of said last one of said lines of display data is stored in said last data storage location of a selected row of said second bank of random access memory devices;
• store a following said line of data in said sequenced lines of display data in a third one of said banks of random access memory devices, a first word of said following line of display data being stored in a location in a row in said third bank of random access memory devices other than said first row of the third bank of random access memory devices;
• and
• store a subsequent line of display data of said sequenced lines of display data being stored in said third bank of random access memory device such that a said word of said subsequent line of display data is stored in said last data storage location of said last row of said third bank of random access memory devices and a next word of said sequenced words of said subsequent line of display data is stored in said first data storage location in said first row of the third bank of random access memory devices.

A graphics processing system comprising:

• a host processing system for determining the contents of a selected visual display to be presented on a video display unit as a plurality of pixels;
• a display buffer comprising a plurality of banks of video random access memory devices, each said bank of video random access memory devices having a plurality of ordered rows of data storage locations including a first row and a last row, said storage locations of each row ordered and including a first data storage location and a last data storage location;
• a graphics processor coupled to said host processing system and said display buffer for generating said selected visual display as a plurality of sequenced lines of display data in said display buffer, each said sequenced line of display data comprising a plurality of sequenced data words defining a said pixel, said graphics processor operable to:
• store sequenced lines of display data in contiguous locations in a first one of said banks of video random access memory devices, a first word of a first one of said sequenced lines of display data being stored in a location offset from said first data storage location of said first row of said first bank of video random access memory device such that a last word of a last line of display data being stored in said first bank of video random access memory devices is stored in said last data storage location of said last row of said first bank of video random access memory devices;
• store a next line of display data in said sequenced lines of display data in said first row of a second one of said banks of video random access memory devices, a first word of said next line of display data being stored in said first data storage location of said first row of said second bank of video random access memory devices;
• store a last line of display data of said sequenced lines of display data being stored in said second bank of video random access memory devices such that a last word of said last one of said lines of display data is stored in said last data storage location of a selected row of said second bank of video random access memory devices;
• store a following said line of display data of said sequenced lines of display data in a third one of said banks of video random access memory devices, a first word of said following line of display data being stored in a location in a row in said third bank of video random access memory devices other than said first row of the third bank of video random access memory devices;
• and
• store a subsequent line of display data of said sequenced lines of display data being stored in said third bank of video random access memory devices such that a said word of said subsequent line of display data is stored in said last data storage location of said last row of said third bank of video random access memory device and a next word of said sequenced words of said subsequent line of display data is stored in said first data storage location in said first row of the third bank of video random access memory devices;
• and
• backend circuitry coupled to said graphics processor and
• said display buffer for driving said display unit.

A method of storing a plurality of sequenced data lines, each data line comprising a plurality of sequenced data words including a first word and a last word, in a memory system comprising a plurality of memory banks, each bank having a plurality of ordered rows of data storage locations including a first row and a last row, the storage locations of each row ordered and including a first and a last storage location, the method comprising the steps of:

• storing at least a portion of a first one of the sequenced data lines in the first row of a first one of the memory banks, the first word of the first line being stored in a location offset from the first location of the first row such that the last word of a last line being stored in the first bank is stored in the last location of the last row of the first memory bank;
• storing the next line in the sequence of lines in the first row of a second memory bank, the first word of the next line stored in the first location of the first row of the second bank;
• storing a last one of ones of the lines being stored in the second bank in the locations of the second bank such that the last word of the last line being stored in the second bank is stored in the last location of a selected row;
• storing the following line in the sequence of lines in a third memory bank, the first word of the following line being stored in a location in a row other than said first row of the third memory bank;
• and
• storing a subsequent line of ones of the lines being stored in the third memory bank in the locations of the third memory bank such that a word of the subsequent line is stored in the last location of the last row of the third bank and the next word in the sequence of words of the subsequent line is stored in the first location in the first row of the third memory bank.