Topography for integrated circuit operational amplifier

A high speed integrated circuit operational amplifier chip including first, second, third and fourth edges, the operational amplifier chip comprising in combination:

• (a) a plurality of bonding pads, including an inverting input bonding pad located in a first corner formed by the first and fourth edges, a non-inverting input bonding pad located in a second corner formed by the first and second edges, a V.sub.EE bonding pad located in a third corner formed by the second and third edges, a V.sub.CC bonding pad located in a fourth corner formed by the third and fourth edges, and an output bonding pad located along the third edge between the V.sub.EE and V.sub.CC bonding pads approximately equal size first and second half sections of the operational amplifier chip being located on opposite sides of a thermal centerline parallel to the second and fourth edges;
• (b) an output driver circuit located adjacent to the output bonding pad and disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline, wherein the output driver circuit includes first and second parallel-connected NPN output transistors and first and second parallel-connected PNP output transistors, the first and second PNP output transistors being symmetrically disposed immediately adjacent to and on opposite sides of the thermal centerline, the first and second NPN output transistors being disposed symmetrically about the thermal centerline immediately adjacent to the first and second PNP output transistors, respectively;
• (c) a low gain differential input circuit located adjacent to the first edge and disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of various matched transistors in the low gain differential input circuit to isotherms produced by the differential heating;
• (d) a plurality of low gain amplification circuit transistors located adjacent to the low gain differential input circuit and disposed along the thermal centerline between the low gain differential input circuit and the output driver circuit to provide approximately balanced response to the low gain amplification circuit transistors to differential heating by the output driver circuit;
• and
• (e) compensated bias current circuitry located along the fourth edge and adjacent to the low gain amplification circuit transistors and the output driver circuit.