Semiconductor device having supply voltage deboosting circuit

A semiconductor device, comprising:

• a reference potential generating circuit for receiving a power supply voltage and for outputting a reference potential;
• a differential amplifier for receiving the reference potential and a first signal, said differential amplifier comparing the first signal with the reference potential, and outputting a second signal based on a result of the comparison;
• an output circuit for receiving the second signal, said output circuit generating and outputting an internal power supply voltage based on the second signal from an internal power supply voltage terminal disposed therein, and outputting the first signal derived from the internal power supply voltage to the differential amplifier;
• a first control circuit having an input terminal connected to a bonding pad, said first control circuit outputting a control signal to control operations of the reference potential generating circuit, the differential amplifier, and the output circuit;
• and
• a second control circuit having a fuse and a resistive element connected in series between a power supply voltage terminal and a ground terminal, two inverters connected in series and having an input terminal connected to a node connecting the fuse and the resistive element, a transistor connected between the power supply voltage terminal and the internal power supply terminal of the output circuit, said transistor having a gate terminal that is connected to an output terminal of the inverters,
• wherein, in a case when the bonding pad is connected to the power supply voltage terminal and the fuse is blown, the reference potential generating circuit, the differential amplifier, and the output circuit do not operate as controlled by the control signal, and the transistor of the control circuit turns on so that the internal power supply voltage terminal is connected to the power supply voltage terminal such that the output circuit outputs the power supply voltage as the internal power supply voltage.

A semiconductor device, comprising:

• a reference potential generating circuit for receiving a power supply voltage and for outputting a reference potential;
• a differential amplifier connected to the reference potential generating circuit, said differential amplifier receiving the reference potential and a first signal, said differential amplifier comparing the first signal with the reference potential, and outputting a second signal based on a result of the comparison;
• an output circuit having an internal power supply voltage terminal connected to a first bonding pad, said output circuit receiving the second signal, said output circuit outputting an internal power supply voltage from the internal power supply voltage terminal disposed therein, and outputting the first signal based on the internal power supply voltage to the differential amplifier;
• and
• a control circuit having an input terminal connected to a second bonding pad, said control circuit outputting a control signal to control operations of the reference potential generating circuit, the differential amplifier, and the output circuit,
• wherein, in a case when the first bonding pad is connected to a power supply voltage terminal and the second bonding pad is connected to a ground terminal, the reference potential generating circuit, the differential amplifier, and the output circuit do not operate as controlled by the control signal, and the power supply voltage is output as the internal power supply voltage from the internal power supply terminal.

A semiconductor device, comprising:

• a detecting circuit for receiving a power supply voltage and for outputting a first detection signal when the power supply voltage is lower than a predetermined level, said detecting circuit outputting a second detection signal when the power supply voltage is greater than or equal to the predetermined level;
• an output transistor connected between a power supply voltage terminal and an output terminal of the semiconductor device, said output transistor having a gate terminal that is connected to a control terminal of the semiconductor device;
• a control circuit connected between an output terminal of the detecting circuit and the control terminal, said control circuit outputting an off signal to the control terminal to turn the output transistor off when the detecting circuit outputs the second detection signal;
• a reference potential generating circuit connected to the control circuit, said reference potential generating circuit receiving the power supply voltage and outputting a reference potential signal;
• a differential amplifier connected to the control circuit and the reference potential generating circuit, said differential amplifier comparing a first signal with the reference potential signal and outputting a second signal to the control terminal in order to control a conductive resistance of the output transistor when the detecting circuit outputs the first detection signal, wherein the differential amplifier does not operate when the detecting circuit outputs the second detection signal;
• and
• a resistive divider having a plurality of resistive elements connected in series between the output terminal of the semiconductor device and an output terminal of an inverter which has an input terminal connected to the output terminal of the detecting circuit, wherein a conjunction node of the resistive elements operates as an output terminal for outputting the first signal when the detecting circuit outputs the first detection signal.

A semiconductor device, comprising:

• a detecting circuit for receiving a power supply voltage and for outputting a first detection signal when the power supply voltage is lower than a predetermined level, said detecting circuit outputting a second detection signal when the power supply voltage is greater than or equal to the predetermined level;
• a sense circuit for receiving data transferred from a pair of bit lines, for sensing the data, and for outputting a first and a second signal as a result thereof;
• a first inverter having a first P-channel transistor with a gate terminal which receives the first signal and a first N-channel transistor with a gate terminal which receives the second signal, wherein said first P-channel transistor and said first N-channel transistor are connected in series between a power supply voltage terminal and a ground terminal, and wherein a conjunction node of the first P-channel transistor and the second N-channel transistor is connected to an output terminal of the semiconductor device;
• and
• a second inverter connected to the detecting circuit, said second inverter having a second P-channel transistor with a gate terminal which receives the first signal, a second N-channel transistor with a gate terminal which receives one of the first detection signal and the second detection signal, a third N-channel transistor with a gate terminal which receives one of the first detection signal and the second detection signal, and a fourth N-channel transistor with a gate terminal which receives the second signal, wherein the first, second, third and fourth N-channel transistors are connected in series between the power supply voltage terminal and a ground terminal, and wherein a conjunction node of the second N-channel transistor and the third N-channel transistor is connected to the output terminal of the semiconductor device,
• wherein the first and second inverters output data in accordance with the first and second signals in a first case when the detecting circuit outputs the first detection signal, and the second inverter does not operate and the first inverter outputs data in accordance with the first and second signals in a second case when the detecting circuit outputs the second detection signal.

A semiconductor device, comprising:

• a detecting circuit for receiving a power supply voltage and for outputting a first detection signal when the power supply voltage is lower than a first predetermined level, the detecting circuit outputting a second detection signal when the power supply voltage is greater than or equal to the first predetermined level;
• a reference potential generating circuit for receiving the power supply voltage from the detecting circuit and for outputting a reference potential having a second predetermined level,
• an internal supply voltage deboosting circuit for receiving the power supply voltage from the detecting circuit, said internal supply voltage deboosting circuit deboosting the power supply voltage to a third predetermined level and outputting the deboosted power supply voltage as an internal supply voltage;
• a first control circuit having a transistor being controlled by one of the first detection signal and the second detection signal, the first control circuit being connected between an output terminal of the internal supply voltage deboosting circuit and an output terminal of the reference potential generating circuit, wherein, when the detecting circuit outputs the first detection signal, the transistor turns on and outputs the internal supply voltage outputted from the internal supply voltage deboosting circuit, and when the detecting circuit outputs the second detection signal, the transistor turns off and the reference potential is outputted;
• a second control circuit for receiving an externally supplied enable signal and for outputting a first signal as a result thereof;
• and
• a third control circuit having a first P-channel transistor being controlled by the first signal and a second P-channel transistor with a gate terminal connected to a first node connected in parallel between the power supply voltage terminal and the first node, a first N-channel transistor connected between the first node and a ground terminal and being controlled by one of the internal supply voltage and the reference potential, and a third P-channel transistor with a gate terminal connected to the first node connected between the power supply voltage terminal and a second node for enabling a sense amplifier, wherein when the first control circuit outputs the terminal power supply voltage and the second control circuit outputs the first signal, the first P-channel transistor turns on, a conductive resistance of the first N-channel transistor becomes a first value, and the third P-channel transistor outputs a first enable signal to the sense amplifier via the second node, and wherein when the first control circuit outputs the reference potential and the second control circuit outputs the first signal, the first P-channel transistor turns on, a conductive resistance of the first N-channel transistor becomes a second value being greater than the first value, and the third P-channel transistor outputs a second enable signal having a voltage being lower than that of the first enable signal to the sense amplifier via the second node.

A semiconductor device, comprising:

• a control circuit having a control input terminal connected to a bonding pad, a discharge means for discharging the control input terminal, two inverters connected in series between the control input terminal and a control output terminal, wherein in a case when the bonding pad is connected to a power supply voltage terminal, a first control signal is output from the control output terminal, and in the case that the bonding pad is not connected to the power supply voltage terminal and the control terminal is not supplied with the power supply voltage and is discharged by the discharging means, a second control signal is output from the control output terminal;
• a first reference potential generating circuit for outputting a first reference potential when the control circuit outputs the first control signal;
• a second reference potential generating circuit for outputting a second reference potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second reference potential generating circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first reference potential when the control circuit outputs the first control signal, and the switching circuit receiving and outputting the second reference potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a control circuit having a fuse connected to a power supply voltage terminal and a node, a discharge means for discharging the node, an inverter connected between the node and a control output terminal, wherein in a first case when the fuse is not blown, a first control signal is output from the control output terminal, and in a second case when the fuse is blown and the node is discharged by the discharge means, a second control signal is output from the control output terminal;
• a first reference potential generating circuit for outputting a first reference potential when the control circuit outputs the first control signal;
• a second reference potential generating circuit for outputting a second reference potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second reference potential generating circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first reference potential when the control circuit outputs the first control signal, and the switching circuit receiving and outputting the second reference potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a control circuit having a control input terminal connected to a bonding pad, a charge means for charging the control input terminal, an inverter connected between the control input terminal and a control output terminal, wherein in a first case when the bonding pad is not connected to a ground terminal and the control input terminal is charged by the charge means, a first control signal is output from the control output terminal, and in a second case when the bonding pad is connected to the ground terminal, a second control signal is output from the control output terminal;
• a first reference potential generating circuit for outputting a first reference potential when the control circuit outputs the first control signal;
• a second reference potential generating circuit for outputting a second reference potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second reference potential generating circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first reference potential when the control circuit outputs the first control signal, and the switching circuit receiving and outputting the second reference potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a control circuit having a control input terminal connected to a bonding pad, a discharge means for discharging the control input terminal, two inverters connected in series between the control input terminal and a control output terminal, wherein in a first case when the bonding pad is connected to the power supply voltage terminal, a first control signal is output from the control output terminal, and in a second case when the bonding pad is not connected to the power supply voltage terminal and the control terminal is not supplied with the power supply voltage and is discharged by the discharge means, a second control signal is output from the control output terminal;
• a first substrate potential generating circuit for outputting a first substrate potential when the control circuit outputs the first control signal;
• a second substrate potential generating circuit for outputting a second substrate potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second substrate potential generating circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first substrate potential when the control circuit outputs the first control signal, and the switching circuit receiving and outputting the second substrate potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a control circuit having a fuse connected to a power supply voltage terminal and a node, a discharge means for discharging the node, an inverter connected between the node and a control output terminal, wherein in a first case when the fuse is not blown, a first control signal is output from the control output terminal, and in a second case when the fuse is blown and the node is discharged by the discharge means, a second control signal is output from the control output terminal;
• a first substrate potential generating circuit for outputting a first substrate potential when the control circuit outputs the first control signal;
• a second substrate potential generating circuit for outputting a second substrate potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second substrate potential generating circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first substrate potential when the control circuit outputs the first control signal, and the switching circuit receiving and outputting the second substrate potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a control circuit having a control input terminal connected to a bonding pad, a charge means for charging the control input terminal, an inverter connected between the control input terminal, an inverter connected between the control output terminal and a output terminal, wherein in a first case when the bonding pad is not connected to a ground terminal and the control input terminal is charged by the charge means, a first control signal is output from the control output terminal, and in a second case when the bonding pad is connected to the ground terminal, a second control signal is output from the control output terminal;
• a first substrate potential generating circuit for outputting a first substrate potential when the control circuit outputs the first control signal;
• a second substrate potential generating circuit for outputting a second substrate potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second substrate potential generating circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first substrate potential when the control circuit outputs the first control signal, and switching circuit receiving and outputting the second substrate potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a control circuit having a control input terminal connected to a bonding pad, a discharge means for discharging the control input terminal, two inverters connected in series between the control input terminal and a control output terminal, wherein in a first case when the bonding pad is connected to the power supply voltage terminal, a first control signal is output from the control output terminal, and in a second case when the bonding pad is not connected to the power supply voltage terminal and the control terminal is not supplied with the power supply voltage and is discharged by the discharge means, a second control signal is output from the control output terminal;
• a first booster circuit for outputting a first boosted potential when the control circuit outputs a first control signal;
• a second booster circuit for outputting a second boosted potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second booster circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first boosted potential when the control circuit outputs the first control signal, and the switching circuit receiving and outputting the second boosted potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a control circuit having a fuse connected to a power supply voltage terminal and a node, a discharge means for discharging the node, an inverter connected between the node and a control output terminal, wherein in a first case when the fuse is not blown, a first control signal is output from the control output terminal, and in a second case when the fuse is blown and the node is discharged by the discharge means, a second control signal is output from the control output terminal;
• a first booster circuit for outputting a first boosted potential when the control circuit outputs a first control signal;
• a second booster circuit for outputting a second boosted potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second booster circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first boosted potential when the control circuit outputs the first control signal, and the switching circuit receiving and outputting the second boosted potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a control circuit having a control input terminal connected to a bonding pad, a charge means for charging the control input terminal, an inverter connected between the control input terminal and a control input terminal, wherein in a first case when the bonding pad is not connected to a ground terminal and the control input terminal is charged by the charge means, a first control signal is output from the control output terminal, and in a second case when the bonding pad is connected to the ground terminal, a second control signal is output from the control output terminal;
• a first boosted potential generating circuit for outputting a first boosted potential when the control circuit outputs the first control signal;
• a second boosted potential generating circuit for outputting a second boosted potential when the control circuit outputs the second control signal;
• and
• a switching circuit connected to the first and second boosted potential generating circuits, the switching circuit being controlled by one of the first and second control signal, the switching circuit receiving and outputting the first boosted potential when the control circuit outputs the first control signal, and the switching circuit receiving and outputting the second boosted potential when the control circuit outputs the second control signal.

A semiconductor device, comprising:

• a first detecting circuit for receiving a power supply voltage and for outputting a first detection signal when the power supply voltage is lower than a predetermined level, said first detecting circuit outputting a second detection signal when the power supply voltage is greater than or equal to the predetermined level;
• a second detecting circuit for receiving a power supply voltage and for outputting a third detection signal irrespective of a level of the power supply voltage;
• a first output transistor connected between a power supply voltage terminal and an output terminal of the semiconductor device, said first output transistor having a gate terminal that is connected to a first control terminal of the semiconductor device;
• a second output transistor connected between a power supply voltage terminal and an output terminal of the semiconductor device, said second output transistor having a gate terminal that is connected to a second control terminal of the semiconductor device;
• a first control circuit connected between an output terminal of the first detecting circuit and the first control terminal, said first control circuit outputting an on signal to the first control terminal to turn the first output transistor on when the first detecting circuit outputs the first detection signal, said first control circuit outputting an off signal to the first control terminal to turn the first output transistor off when the first detecting circuit outputs the second detection signal;
• a second control circuit connected between an output terminal of the second detecting circuit and the second control terminal, said second control circuit outputting an on signal to the second control terminal to turn the second output transistor on when the second detecting circuit outputs the third detection signal;
• a reference potential generating circuit for receiving the power supply voltage and for outputting a reference potential;
• a first differential amplifier for comparing a first signal with the reference potential output from the reference potential generating circuit and for outputting a second signal to the first control terminal in order to control a conductive resistance of the first output transistor when the first detecting circuit outputs the first detection signal, wherein the differential amplifier does not operate when the first detecting circuit outputs the second detection signal;
• a second differential amplifier for comparing a third signal with the reference potential output from the reference potential generating circuit and for outputting a fourth signal to the second control terminal in order to control a conductive resistance of the second output transistor when the second detecting circuit outputs the third detection signal;
• a first resistive divider having a plurality of first resistive elements connected in series between the output terminal of the semiconductor device and an output terminal of a first inverter which has an input terminal connected to the output terminal of the first detecting circuit, wherein a conjunction node of the first resistive elements operates as an output terminal for outputting the first signal when the first detecting circuit outputs the first detection signal;
• and
• a second resistive divider having a plurality of second resistive elements connected in series between the output terminal of the semiconductor device and an output terminal of a second inverter which has an input terminal connected to the output terminal of the second detecting circuit, wherein a conjunction node of the second resistive elements operates as an output terminal for outputting the third signal when the second detecting circuit outputs the third detection signal.