Level shifter with improved rejection of voltage variations

A level shifter for shifting a digital signal from a digital signal input voltage to a digital signal output voltage, comprising:

• a trigger for triggering a pulse at a transition of the digital signal between an input supply voltage and an input reference voltage;
• a latch for switching the digital signal to one of an output supply voltage and an output reference voltage in response to each pulse from the trigger and holding the digital signal at that voltage;
• a first half-shifter connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input supply voltage to the input reference voltage;
• and
• a second half-shifter connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input reference voltage to the input supply voltage,
• said first and second half-shifters each comprising a selector circuit with plural current mirrors connected to a current source for providing a current to said current mirrors responsive to receipt of the pulse, said current source comprising,
• a first transistor having a control terminal connected to the input supply voltage and a source terminal that is an open circuit when a voltage on the source terminal is less than the input supply voltage, and
• a second transistor having a control terminal connected to receive the pulse and operating terminals connected between said source terminal of said first transistor and the input reference voltage thereby reducing a capacitance in said selector circuit that induces the voltage variations.

A level shifter for shifting a digital signal from a digital signal input voltage to a digital signal output voltage, comprising:

• a trigger for triggering a pulse at a transition of the digital signal between an input supply voltage and an input reference voltage;
• a latch for switching the digital signal to one of an output supply voltage and an output reference voltage in response to each pulse from the trigger and holding the digital signal at that voltage;
• a first half-shifter connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input supply voltage to the input reference voltage;
• and
• a second half-shifter connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input reference voltage to the input supply voltage,
• wherein said first and second half-shifters each comprise a selector circuit with plural series-connected current mirrors for preventing an error current induced by a capacitance in said selector circuit from providing voltage variations that would cause said latch to switch, said series connected current mirrors providing two copies of the error current in directions that do not cause the latch to switch, thereby overriding the error current.

A level shifter for shifting a digital signal from a digital signal input voltage to a digital signal output voltage, comprising:

• a trigger for triggering a pulse at a transition of the digital signal between an input supply voltage and an input reference voltage;
• a latch for switching the digital signal to one of an output supply voltage and an output reference voltage in response to each pulse from the trigger and holding the digital signal at that voltage;
• a first half-shifter connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input supply voltage to the input reference voltage;
• and
• a second half-shifter connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input reference voltage to the input supply voltage,
• wherein said first and second half-shifters each comprise a selector circuit with plural current mirrors and one of said plural current mirrors comprises a load transistor for sensing a voltage related to the pulse, and further comprising a second diode for diverting current from a drain of said load transistor, thereby reducing a charge stored in a junction of said load transistor and reducing a time for discharging the stored charge when the output reference voltage changes from a falling voltage to a rising voltage.

A level shifter for shifting a digital signal from a digital signal input voltage to a digital signal output voltage comprising:

• a trigger for triggering a pulse at a transition of the digital signal between an input supply voltage and an input reference voltage;
• a latch for switching the digital signal to one of an output supply voltage and an output reference voltage in response to each pulse from the trigger and holding the digital signal at that voltage;
• a first half-shifter connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input supply voltage to the input reference voltage;
• and
• a second half-shifter connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input reference voltage to the input supply voltage,
• wherein said first and second half-shifters each comprise a selector circuit with plural current mirrors and one of said plural current mirrors comprises a load transistor for sensing a voltage related to the pulse, and further comprising a parasitic transistor for selectively diverting current from a drain of said load transistor, thereby selectively reducing a charge stored in a junction of said load transistor in one of said first and second half-shifters so that a voltage variation caused by a difference between times for discharging the stored charge in said load transistors in said first and second half-shifters does not cause said latch to switch when the output reference voltage changes from a falling voltage to a rising voltage.

A level shifter for shifting a digital signal from a digital signal input voltage to a digital signal output voltage, comprising:

• a trigger for triggering a pulse at a transition of the digital signal between an input supply voltage and an input reference voltage;
• a latch for switching the digital signal to one of an output supply voltage and an output reference voltage in response to each pulse from the trigger and holding the digital signal at that voltage;
• a first half-shifter comprising plural current mirrors connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input supply voltage to the input reference voltage;
• a second half-shifter comprising plural current mirrors connected between said trigger and said latch for providing the pulse to said latch when the digital signal transitions from the input reference voltage to the input supply voltage;
• and
• a logic circuit connected between said trigger and said first and second half-shifters for comparing a state of said latch to a state of the digital signal input voltage, and for providing a corrective signal when the two states are different,
• said logic circuit comprising a plurality of transistors that are off when the two states are the same so that current flows through said logic circuit is prevented until the two states are different.