Delay circuit, oscillation circuit and semiconductor memory device

A delay circuit having a standby state and an active state and configured to output at least one delayed signal obtained by delaying an input signal, comprising:

• a storage circuit comprising,
• a constant voltage generator for generating a first voltage when the delay circuit enters the active state which occurs when the input signal changes from a first level to a second level,
• at least one constant-current generating section configured to generate at least one current proportional to a difference between said first voltage and a first supply voltage, and
• at least one capacitor comprising,
• a first terminal set to at least one of the first supply voltage or a second supply voltage, and
• a second terminal set respectively to said second supply voltage or said first supply voltage while the delay circuit is in said standby state, and respectively charged or discharged to a second voltage by the current provided by said constant current generating section while in the active state;
• at least one amplifier circuit configured to output the delayed signal as an output signal by amplifying a difference between the first voltage and the second voltage;
• and
• at least one feed-back means for preventing a DC current from flowing in said at least one amplifier circuit after said output signal is inverted and for keeping a logic level of the output signal constant until said input signal returns to said first level.