Voltage-independent super voltage detection circuit

A super voltage detection circuit comprising:

• (a) an input terminal to which a super voltage may be selectively applied;
• (b) first and second pluralities of series-coupled N-channel diodes;
• (c) first and second current-limiting devices;
• (d) a reference voltage node coupled to both ground potential through said first plurality of series-coupled diodes, and to a power supply voltage through said first current-limiting device;
• and
• (e) an insulated-gate P-channel field-effect transistor having its gate coupled to the reference voltage node, its source region coupled to said input terminal through said second plurality of series-coupled diodes, and its drain region coupled to ground potential through said second current-limiting device, the potential on said drain region being indicative of the presence of a super voltage on said input terminal.

A super voltage detection circuit comprising:

• (a) an input terminal to which a super voltage may be selectively applied;
• (b) first and second diode sets, each set having at least one diode;
• (c) first and second current limiting devices;
• (d) a reference voltage node to which a reference voltage is supplied, said reference voltage node being coupled to both a first voltage supply bus via said first diode set and to a second voltage supply bus via said first current limiting device;
• (e) a field-effect transistor having its gate coupled to the reference voltage node, a first source/drain region coupled to said input terminal via said second diode set, and a second source/drain region coupled to said first voltage supply bus via said second current limiting device, the potential on said second source/drain region being indicative of the presence of a super voltage on said input terminal.

A super voltage detection circuit comprising:

• (a) an input terminal to which a super voltage may be selectively applied;
• (b) a first current limiting device;
• (c) a reference voltage node to which a reference voltage is supplied, said reference voltage node being coupled to a first voltage supply bus via a first diode set, said first diode set having at least one diode, and to a second voltage supply bus through a second current limiting device;
• (d) a field-effect transistor having a gate coupled to the reference voltage node, a first source/drain region coupled to said input terminal, and a second source/drain region coupled to said first voltage supply bus via the current limiting device, the potential on said second source/drain region being indicative of the presence of a super voltage on said input terminal.