CMOS sense amplifier

A sense amplifier comprising:

• a sense amplifier latch formed from first and second CMOS gates serially connected between an amplifier voltage source terminal and a common node and third and fourth CMOS gates serially connected between amplifier voltage source terminal and the common node, the sense amplifier latch having a first latch node between the first and second CMOS gates and a second latch node between the third and fourth CMOS gates, the first latch node connected to a gate terminal of each of the first and second CMOS gates and the second latch node connected to a gate terminal of each of the third and fourth CMOS gates;
• charge circuitry responsive to a charge control signal for periodically charging the first and second latch nodes;
• a latch input gate connected between the first latch node and an amplifier ground terminal and a latch reference gate connected between the second latch node and the amplifier ground terminal;
• a source of reference voltage connected to the latch reference gate and responsive to an amplifier enable signal to generate a reference voltage signal of a predetermined value;
• an input conductor connected to the latch input gate providing an input signal on the input conductor having a high voltage level state greater than the predetermined value and a low voltage level value lower than the predetermined state;
• a latch enable gate connected between the common node and the amplifier ground terminal and responsive to the amplifier enable signal to connect the common node to the amplifier ground terminal;
• the input gate responsive to the input signal to discharge the first node when a high voltage level state input signal is provided on the input conductor and the sense amplifier latch responsive to the discharge of the first node to assume a first binary state;
• the latch reference gate responsive to the reference voltage signal to discharge the second node when a low voltage level state input signal is provided on the input conductor and the sense amplifier latch responsive to the discharge of the second node to assume a second binary state;
• a sense amplifier output terminal and an output amplification circuit having an input terminal connected to a selected one of the first and second latch nodes and having an output terminal connected to the sense amplifier output terminal for amplifying a signal representative of the binary states of the selected one of the first and second latch nodes.

A method of sensing the state of an input signal in a sense amplifier, the method comprising the steps of:

• providing a sense amplifier latch formed from first and second CMOS gates serially connected between an amplifier voltage source terminal and a common node and third and fourth CMOS gates serially connected between the amplifier voltage source terminal and the common node, the sense amplifier latch having a first charged latch node between the first and second CMOS gates and a second charged latch node between the third and fourth CMOS gates, the second latch node connected to a gate terminal of each of the first and second CMOS gates and the second latch node connected to a gate terminal of each of the third and fourth CMOS gates;
• connecting a first discharge gate to the first latch node and connecting a second discharge gate to the second latch node;
• applying an input signal varying between first and second signal values over time to the first discharge gate;
• applying a reference signal having a predetermined signal value falling between the first and second signal values to the second discharge gate;
• discharging the first latch node via the first discharge gate when the value of the input signal is greater than the predetermined value;
• and
• discharging the second latch node via the second discharge gate when the value of the input signal is less than the predetermined.

A sense amplifier comprising:

• an amplifier input terminal for connection to a memory array output terminal;
• a latch formed from interconnected CMOS gates and having first and second latch nodes;
• charge circuitry for periodically charging the latch nodes;
• an amplifier ground terminal;
• a latch input gate connected between the first latch node and the amplifier ground terminal and having a control terminal connected to the amplifier input terminal;
• a source of reference potential independent of the memory array and generating a reference voltage of a predetermined value;
• a latch reference gate connected between the second latch node and the amplifier ground terminal and having a control input terminal connected to the source of reference potential;
• the latch input gate operative to discharge the first node when the voltage level of the input signal on the amplifier input terminal is greater than the predetermined value and the latch reference gate operative to discharge the second node when the voltage level of the input signal on the amplifier input terminal is smaller than the predetermined value;
• a latch enable gate connected between the latch and the amplifier ground terminal;
• and
• latch enable circuitry responsive to an enable input signal to activate the input gate and the latch reference gate prior to activating the latch enable gate.

A sense amplifier for connection to a memory array output terminal and comprising:

• a sense amplifier latch formed from first and second CMOS gates serially connected between an amplifier voltage source terminal and a common node and third and fourth CMOS gates serially connected between amplifier voltage source terminal and the common node, the sense amplifier latch having a first latch node between the first and second CMOS gates and a second latch node between the third and fourth CMOS gates, the first latch node connected to a gate terminal of each of the first and second CMOS gates and the second latch node connected to a gate terminal of each of the third and fourth CMOS gates;
• charge circuitry responsive to a charge control signal for periodically charging the first and second latch nodes;
• an amplifier ground terminal;
• a latch input gate connected between the first latch node and the amplifier ground terminal;
• a latch reference gate having a control input terminal and connected between the second latch node and the amplifier ground terminal;
• a source of reference voltage independent of the memory array and connected to the control input terminal of the latch reference gate and responsive to an amplifier enable signal to generate a reference voltage signal of a predetermined value;
• an input conductor connected to the latch input gate providing an input signal on the input conductor having a high voltage level state greater than the predetermined value and a low voltage level state less than the predetermined value;
• a latch enable gate connected between the common node and the amplifier ground terminal and responsive to the amplifier enable signal to connect the common node to the amplifier ground terminal;
• the latch input gate responsive to the input signal to discharge the first node when a high voltage level state input signal is provided on the input conductor and the sense amplifier latch responsive to the discharge of the first node to assume a first binary state;
• the latch reference gate responsive to the reference voltage signal to discharge the second node when a low voltage level state input signal is provided on the input conductor and the sense amplifier latch responsive to the discharge of the second node to assume a second binary state;
• a sense amplifier output terminal;
• and
• an output amplification circuit having an input terminal connected to a selected one of the first and second latch nodes and having an output terminal connected to the sense amplifier output terminal for amplifying a signal representative of the binary states of the selected one of the first and second latch nodes.