Emitter coupled logic circuit with MOS differential stage
AssigneeSGS-Thomson Microelectronics S.A.
InventorsPatrick Bernard, Didier Belot, Jacques Quervel
Life of this patent
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Abstract
A logic circuit has at least one first differential stage made of bipolar transistors operating in linear mode. The first differential stage is connected in a branch of a second differential stage biased by a current source. The second stage and the current source are made of MOS transistors.
Claims34
A logic circuit comprising:
- a first differential stage including a plurality of bipolar transistors operating in a linear mode, each of the plurality of bipolar transistors having a base terminal, a collector terminal, and an emitter terminal, each of the emitter terminals being coupled together;
- a second differential stage having a branch that is coupled to the emitter terminals of the first differential stage, the second differential stage including MOS transistor having a gate terminal, a source terminal and a drain terminal;
- and
- a current source coupled to the second differential stage, that biases the first differential stage so that each of the plurality of bipolar transistors operate in the linear mode, the current source including MOS transistors;
- wherein gates of the MOS transistors of the second stage receive the same voltage levels as the base terminals of the bipolar transistors of the first stage.
An emitter coupled logic device comprising:
- a first differential stage including a first bipolar transistor having a collector, a base, and an emitter, and a second bipolar transistor having a collector, a base, and an emitter coupled to the emitter of the first bipolar transistor;
- a constant current source including a MOS transistor that couples the emitter of the first bipolar transistor to a reference voltage;
- and
- a second differential stage that couples the emitter of the first bipolar transistor to the constant current source, the second differential stage including a plurality of MOS transistors coupled together.
A method of biasing a differential stage of an emitter coupled logic device, the differential stage including a plurality of bipolar transistors having emitter terminals coupled together, the method comprising the steps of:
- coupling a MOS transistor to the differential stage;
- coupling a second terminal of the MOS transistor to a first reference voltage;
- providing a second reference voltage to a gate terminal of the MOS transistor, so that the MOS transistor sources current from the differential stage sufficient to keep the bipolar transistors of the differential stage in one of an off mode and a linear mode;
- and
- coupling a second differential stage including a plurality of MOS transistors between the differential stage and the MOS transistor.
An improved emitter coupled logic device of the type having a first differential stage including a first bipolar transistor having an emitter and a second bipolar transistor having an emitter coupled to the emitter of the first bipolar transistor, the improved emitter coupled logic device further including a current source and a second differential stage coupled between the current source and the first differential stage, the improvement comprising:
- a MOS transistor included in the current source;
- wherein the second differential stage includes a plurality of MOS transistors coupled together.
An improved emitter coupled logic device of the type having a first differential stage including a first bipolar transistor having an emitter and a second bipolar transistor having an emitter coupled to the emitter of the first bipolar transistor, the improved emitter coupled logic device further including a constant current source and a second differential stage coupled between the current source and the first differential stage, the improvement comprising:
- a plurality of MOS transistors, coupled together, included in the second differential stage.
An improved emitter coupled logic device of the type having a first differential stage including a first bipolar transistor having an emitter and a second bipolar transistor having an emitter coupled to the emitter of the first bipolar transistor, the improved emitter coupled logic device further including a constant current source and a second differential stage coupled between the current source and the first differential stage, the improved emitter coupled logic device having a minimum supply voltage by which the first bipolar transistor and the second bipolar transistor operate in a linear mode, the improvement comprising:
- means, contained within the second differential stage, for maintaining the first bipolar transistor and the second bipolar transistor in the linear mode while decreasing the minimum supply voltage.
An emitter coupled logic device comprising:
- a first differential stage including a first bipolar transistor having a collector, a base, and an emitter, and a second bipolar transistor having a collector, a base, and an emitter coupled to the emitter of the first bipolar transistor;
- and
- a constant current source including a MOS transistor that couples the emitter of the first bipolar transistor to a reference voltage;
- wherein the first differential stage includes two first differential stages, each of the two first differential stages having a first bipolar transistor having a collector, a base, and an emitter, and a second bipolar transistor having a collector, a base, and an emitter coupled to the emitter of the first bipolar transistor, the collectors of each of the first bipolar transistors being coupled together, the collectors of each of the second bipolar transistors being coupled together;
- and wherein the emitter coupled logic device further comprises a second differential stage including:
- a first MOS transistor having a first terminal coupled to the emitters of the first and second bipolar transistors of one of the two first differential stages, a second terminal coupled to the constant current source, and a gate terminal;
- and
- a second MOS transistor having a first terminal coupled to the emitters of the first and second bipolar transistors of another of the two first differential stages, a second terminal coupled to the constant current source, and a gate terminal;
- wherein the emitter coupled logic device forms a multiplexer having a first input that includes complementary signal terminals respectively connected to the base terminals of the first and second bipolar transistors of the one of the two first differential stages, a second input that includes complementary signal terminals respectively connected to the base terminals of the first and second bipolar transistors of the another of the two first differential stages, a third input that includes complementary signal terminals respectively connected to the gate terminals of the first and second MOS transistors, and an output that includes complementary signal terminals respectively coupled to the collectors of the first and second bipolar transistors of the one of the two first differential stages.
An emitter coupled logic device comprising:
- a first differential stage including a first bipolar transistor having a collector, a base, and an emitter, and a second bipolar transistor having a collector, a base, and an emitter coupled to the emitter of the first bipolar transistor;
- a constant current source including a MOS transistor that couples the emitter of the first bipolar transistor to a reference voltage;
- and
- a second differential stage including:
- a first MOS transistor having a first terminal coupled to the emitters of the first and second bipolar transistors of the first differential stage, a second terminal coupled to the constant current source, and a gate terminal;
- and
- a second MOS transistor having a first terminal coupled to the collector of the second bipolar transistor, a second terminal coupled to the constant current source, and a gate terminal;
- wherein the emitter coupled logic device forms a logic gate having a first input that includes complementary signal terminals respectively connected to the base terminals of the first and second bipolar transistors of, a second input that includes complementary signal terminals respectively connected to the gate terminals of the first and second MOS transistors, and an output that includes complementary signal terminals respectively coupled to the collectors of the first and second bipolar transistors.
Dependencies are inferred from the claim text.