Electronic digital clock distribution system
AssigneeCeridian Corporation
InventorMichael J. Lamatsch
Life of this patent
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Abstract
More particularly, an electronic digital clock distribution system provides a plurality of working rank clock signals to respective ones of a plurality of logic circuits. Each clock signal has a predetermined frequency and each logic circuit requires a working rank clock signal having a predetermined level of electrical power. An oscillator produces a master clock signal at the predetermined frequency and at an electrical power level at least equal to the sum of the power requirements for all working rank clock signals of the plurality of logic circuits. An electronic splitter network is connected to the oscillator to splitting the master clock signal into the plurality of working rank clock signals.
Claims12
An electronic digital clock distribution system for providing a plurality of working rank clock signals to respective ones of a plurality of logic circuits, each clock signal having a predetermined frequency and each logic circuit requiring a working rank clock signal having a predetermined level of electrical power, the system comprising:
- oscillator means for producing a master clock signal having the predetermined frequency and an electrical power level at least equal to the sum of the power requirements for all working rank clock signals of the plurality of logic circuits;
- and
- an electronic splitter network connected to the oscillator means for splitting the master clock signal into the plurality of working rank clock signals.
An electronic digital clock distribution system for providing a plurality of working rank clock signals to respective ones of a plurality of logic circuits, each clock signal having a predetermined frequency, the system comprising:
- an oscillator producing a master clock signal having the predetermined frequency and an electrical power level less than the sum of the power requirements for all working rank clock signals of the plurality of logic circuits;
- a power booster connected to the oscillator for increasing the
- power of the master clock signal to a power level at least equal to the sum of the power requirements for all working rank clock signals of the plurality of logic circuits;
- an electronic splitter network connected to the power booster for splitting the master clock signal into the plurality of working rank clock signals, the electronic splitter network comprising a plurality of ranks of splitter stages, each splitter stage having
- a primary winding having first and second ends and an impedance matching tap,
- an input connected to a first end of the primary winding and arranged to receive a clock signal,
- a plurality of secondary windings coupled to the primary winding, each secondary winding having a first end connected to a respective output to provide a respective output clock signal having a power approximately 1/n the power of the input clock signal, each secondary winding further having a second end connected to the impedance matching tap of the primary winding, and
- a source of bias voltage connected to the second end of the primary winding,
- respective ones of a first group of the logic circuits being connected to respective ones of the outputs of a first splitter stage, and respective ones of a second group of the logic circuits being connected to respective ones of the outputs of a second splitter stage, the logic circuits of the first group being of a first class requiring working rank clock signals having a first predetermined bias level and the logic circuits of the second group being of a second class requiring working rank clock signals having a second predetermined bias level, the source of bias voltage connected to the second end of the primary winding of the first splitter stage having the first predetermined bias level and the source of bias voltage connected to the second end of the primary winding of the second splitter stage having the second predetermined bias level.
Dependencies are inferred from the claim text.