Vertical transistor structure
AssigneeMotorola, Inc.
InventorsKeith E. Witek, Jon T. Fitch, Carlos A. Mazure
Life of this patent
Estimating the term…
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AssigneeMotorola, Inc.
InventorsKeith E. Witek, Jon T. Fitch, Carlos A. Mazure
Estimating the term…
A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.
A vertically raised transistor comprising:
A semiconductor structure comprising:
A semiconductor structure comprising:
Dependencies are inferred from the claim text.