An overvoltage self-protection semiconductor device with a pair of main surfaces, comprising at least three adjacent semiconductor layers including a plurality of first semiconductor layers having a high impurities concentration of first conductivity type formed in spaced relationship with each other on a surface of a second semiconductor layer adjacent to a lower portion of the first semiconductor layers at one of the main surfaces, a third semiconductor layer of a first conductivity type adjacent to a lower surface of said second semiconductor layer, and a fourth semiconductor layer of second conductivity type, said first, second, third and fourth semiconductor layers being formed sequentially, a first electrode being formed on at least one of said first semiconductor layers, and a second electrode being formed on said fourth semiconductor layer,
- wherein said overvoltage self-protection semiconductor device includes an overvoltage protection portion including at least one of said first semiconductor layers which does not have said first electrode formed thereon, said at least one of said first semiconductor layers and said second semiconductor layer making up a pn junction portion having a potential barrier, and wherein a plurality of portions are provided adjacent to said pn junction portion, wherein said plurality of portions do not have said first electrode formed thereon, and wherein said plurality of portions provide regions having a high impurities concentration in the surface of the second semiconductor layer at said one of said main surfaces.