Method of manufacturing a wiring layer for use in a semiconductor device having a plurality of conductive layers

A method of manufacturing a semiconductor memory device, which method comprises:

• forming an insulating layer on a main surface of a semiconductor substrate;
• forming an opening in said insulating layer exposing said main surface of said semiconductor substrate;
• and
• forming a bit line on said insulating layer and contacting a conductive surface of said semiconductor substrate through said opening by:
• forming a first conductive layer of polycrystalline silicon on said insulating layer contacting a conductive surface of said semiconductor substrate;
• forming a second insulating layer on said first conductive layer of polycrystalline silicon;
• patterning said first conductive layer of polycrystalline silicon and said second insulating layer;
• depositing a refractory metal layer on said insulating layer, on said second insulating layer and on said side surfaces of said first conductive layer of polycrystalline silicon;
• heating to form said refractory metal silicide layers only on said side surfaces of said first conductive layer of polycrystalline silicon;
• and
• removing the portions of said refractory metal layer not converted to refractory metal silicide;
• wherein, said bit line comprises a first conductive layer of polycrystalline silicon having an upper surface, a lower surface and a pair of side surfaces between said upper and lower surfaces, and a pair of second conductive layers of a refractory metal silicide formed on said insulating layer contacting said first conductive layer only on said side surfaces.

A method of manufacturing a semiconductor device having a field effect transistor, which method comprises:

• forming a first insulating layer on a main surface of a semiconductor substrate;
• forming a gate electrode on said first insulating layer;
• forming a second insulating layer on said gate electrode;
• and
• forming a wiring layer extending to contact said semiconductor substrate on said second insulating layer by:
• forming a polycrystalline silicon layer on said second insulating layer;
• forming a third insulating layer on said polycrystalline silicon layer;
• patterning said polycrystalline silicon layer and said third insulating layer so that each of said polycrystalline silicon layer and third insulating layer comprises a bottom surface, a top surface, and a pair of side surfaces between said bottom surfaces and said top surfaces, wherein said bottom surface of said third insulating layer is on said top surface of said polycrystalline silicon layer;
• depositing a refractory metal layer on said second insulating layer, on said top surface of said third insulating layer, on said side surfaces of said third insulating layer and on said side surfaces of said polycrystalline silicon layer;
• heating to form said refractory metal silicide layers only on said side surfaces of said polycrystalline silicon layer;
• and
• removing the portions of said refractory metal layer not converted to refractory metal silicide, said wiring layer comprising a polycrystalline silicon layer having an upper surface, a lower surface and a pair of side surfaces between said upper and lower surfaces, and a pair of refractory metal silicide layers formed in contact with said polycrystalline silicon layer only at said pair of side surfaces.