Hardware modeling system and method of use

A method of testing the functionality of an electronic device or circuitry electrically coupled to pin electronics circuitry of a hardware modeling system, comprising the steps of:

• a. reading a test vector from a storage device;
• b. stimulating the electronic device or circuitry with the pin electronics circuitry according to the test vector;
• c. measuring a response by the electronic device or circuitry to the step of stimulating, thereby forming a measured response;
• and
• d. comparing the measured response to a stored predetermined response to determine if the electronic device or circuitry is functional.

A hardware modeling system adapted for coupling to one of a predetermined collection of host computers, the hardware modeling system evaluating a response of an electronic device or circuitry to stimulation from the hardware modeling system, with pins of the electronic device or circuitry being electrically coupled to pin drivers of the hardware modeling system, comprising:

• a. a host network configured for coupling to a host computer for transmitting bi-directionally thereon communications between the hardware modeling system and the host computer;
• b. microprocessor circuitry coupled to the host network for coupling programmed operation of the hardware modeling system;
• c. central timing controller for generating timing signals for controlling timing of operations of the hardware modeling system, the central timing controller coupled to the microprocessor circuitry and a pattern bus for generating sample strobes for sampling outputs of the pins of the electronic device or circuitry and edge strobes for formatting stimulation patterns;
• d. pattern bus coupled to the microprocessor and the central timing controller, the pattern bus having a first mode of operation wherein the pattern bus allows the microprocessor circuitry to access certain circuitry for conducting read and write operations and a second mode of operation wherein the pattern bus presents the stimulation patterns to the pins of the electronic device or circuitry which is electrically coupled to the hardware modeling system;
• e. pattern controller coupled to the pattern bus for controlling stimulation pattern sequencing and delivery of stimulation patterns to the pattern bus;
• f. pattern memory device coupled to the pattern controller for storing the stimulation patterns in the pattern memory device in a plurality of memory bits;
• g. pin electronics circuitry coupled to the pattern bus for driving and sensing the pins of the electronic device or circuitry, and the pin electronics circuitry providing sensing of at least four states of the pins of the electronic device or circuitry;
• and
• h. an adaptor coupled to the pin electronics circuitry and configured for coupling the electronic device or circuitry to the hardware modeling system, the adaptor having circuitry for supporting live-insertion into a powered hardware modeling system.

A hardware modeling system for evaluating a response of an electronic device or circuitry to a stimulation pattern received from the hardware modeling system, with pins of the electronic device or circuitry being electrically coupled to pin drivers of the hardware modeling system, comprising:

• a. a host network configured for coupling to a host computer for transmitting bi-directional communications between the hardware modeling system and the host computer;
• b. a microprocessor coupled for controlling the hardware modeling system;
• c. a central timing controller coupled to the microprocessor for generating timing signals for controlling timing of operations of the hardware modeling system, the central timing controller for generating sample strobes for sampling the outputs of the pins of the electronic device or circuitry and generating edge strobes for formatting the stimulation patterns;
• d. a pattern bus coupled to the central timing controller and the microprocessor, the pattern bus having a first mode of operation wherein the pattern bus allows the microprocessor to access certain circuitry for conducting read and write operations and a second mode of operation wherein the pattern bus is utilized to present the stimulation patterns to the pins of the electronic device or circuitry which is electrically coupled to the hardware modeling system;
• e. a pattern controller coupled to the pattern bus for controlling stimulation pattern sequencing and delivery of stimulation patterns to the pattern bus;
• f. a pattern memory device coupled to the pattern controller for storing the stimulation patterns in the pattern memory device in a plurality of memory bits;
• g. pin electronics circuitry coupled to the pattern bus for driving and sensing the pins of the electronic device or circuitry, and the pin electronics circuitry providing sensing of at least four states of the pins of the electronic device or circuitry;
• and
• h. an adaptor coupled to the pin electronics circuitry and configured for coupling the electronic device or circuitry to the hardware modeling system, the adaptor having circuitry for supporting live-insertion into a powered hardware modeling system.

A hardware modeling system for evaluating an electronic device or circuitry by generating a stimulation pattern, coupling the stimulation pattern to the electronic device or circuitry and sensing a response therefrom, the electronic device or circuitry having a plurality of electrical contacts, and further wherein the hardware modeling system is adapted to be coupled for bi-directional communications to a host network, the hardware modeling system comprising:

• a. a central processing unit (CPU) coupled for controlling the hardware modeling system;
• b. a central timing controller coupled to receive control signals from the CPU for generating timing signals for controlling timing of operations of the hardware modeling system, the central timing controller for generating sample strobes for sampling outputs of the electronic device or circuitry and generating edge strobes for exercising the electronic device or circuitry, the central timing controller also coupled to provide the response to the host network;
• c. a pattern bus coupled to the central timing controller and the microprocessor, the pattern bus having a first mode of operation wherein the pattern bus allows the microprocessor to access certain circuitry for conducting read and write operations and a second mode of operation wherein the pattern bus is utilized to present the stimulation patterns to the pins of the electronic device or circuitry which is electrically coupled to the hardware modeling system;
• d. a pattern generator including:
• (1) a pattern memory device for storing the stimulation pattern;
• and
• (2) a pattern controller coupled for control by the central timing controller for retrieving the stimulation pattern and providing the stimulation pattern to the bus according to the edge strobes;
• and
• e. an interface circuit bi-directionally coupled to receive the stimulation pattern from the bus for providing the stimulation pattern to the electronic device or circuitry and for sensing signals applied by the electronic device or circuitry to the contacts.