Cascode circuit operable at a low working voltage and having a high output impedance
AssigneeNEC Corporation
InventorToshiyuki Etoh
Life of this patent
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AssigneeNEC Corporation
InventorToshiyuki Etoh
Estimating the term…
A cascode circuit includes a source-grounded input NMOS transistor having a gate connected to an input terminal and a drain connected through an output NMOS transistor to an output terminal. An amplification circuit is constructed by a gate-grounded third NMOS transistor having a source connected to the drain of the input transistor, a current mirror circuit consisting of PMOS transistors having an input current path connected to a drain of the third transistor, and a current source connected to an output current path of the constant mirror circuit as a load. An output from the amplification circuit is fed back to a gate of the second transistor. With this arrangement, the cascode circuit can maintain a high output impedance until a minimum output signal voltage reaches around 0.5 V, and can also have a minimum working supply voltage of about 2 V, and at the same time, a circuit construction suitable for IC in the CMOS process.
A cascode circuit comprising:
A cascode circuit comprising:
A cascode circuit comprising:
A cascode circuit comprising:
Dependencies are inferred from the claim text.