Multiple-bit random access memory cell
AssigneeSolidas Corporation
InventorTamio Saito
Life of this patent
Estimating the term…
Abstract
An improved multi-bit memory cell includes a storage capacitor and a switching element coupled to one of the terminals of the capacitor. The switching element includes a first switching component having a positive threshold, and a complementary switching component having a negative threshold. Because the switching element is constructed in this manner, noise generation caused by activation of the switching components is significantly reduced, and cut-off effects are eliminated. Both of these factors contribute to the memory cell's ability to store more bits of information than prior art memory cells.
Claims15
A memory cell for storing a plurality of bits of information comprising:
- a storage capacitor capable of storing one of more than two different voltage levels, said capacitor having a first terminal and a second terminal:
- a switching element comprising:
- a first switching component, having a coupling terminal coupled to the first terminal of said capacitor, a data terminal coupled to a conductive line, and a control terminal coupled to a control line, for selectively coupling said capacitor to said conductive line, said first switching component having a threshold voltage which is positive;
- and
- a complementary switching component, having a coupling terminal coupled to the first terminal of said capacitor, a data terminal coupled to said conductive line, and a control terminal coupled to a second control line, for selectively coupling said capacitor to said conductive line, said complementary switching component having a threshold voltage which is negative;
- and
- a discharge element coupled to the first and second terminals of said capacitor for selectively discharging said capacitor.
A memory, comprising:
- a first bit line;
- a second bit line;
- a first set of multi-bit memory cells coupled to said first bit line;
- a second set of multi-bit memory cells coupled to said second bit line;
- a first dummy cell coupled to said first bit line;
- a second dummy cell coupled to said second bit line;
- and
- a comparator having inputs and an output, said inputs being coupled to said first and second bit lines;
- wherein at least one of said multi-bit memory cells comprises:
- a storage capacitor capable of storing one of more than two different voltage levels, said capacitor having a first terminal and a second terminal;
- and
- a switching element comprising:
- a first switching component, having a coupling terminal coupled to the first terminal of said capacitor, a data terminal coupled one of said bit lines, and a control terminal coupled to a control line, for selectively coupling said capacitor to said one bit line, said first switching component having a threshold voltage which is positive;
- and
- a complementary switching component, having a coupling terminal coupled to the first terminal of said capacitor, a data terminal coupled to said one bit line, and a control terminal coupled to a second control line, for selectively coupling said capacitor to said one bit line, said complementary switching component having a threshold voltage which is negative.
Dependencies are inferred from the claim text.