MPEG video decoder having a high bandwidth memory
AssigneeMatsushita Electric Corporation of America
InventorsLarry Phillips, Shuji Inoue, Edwin R. Meyer
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AssigneeMatsushita Electric Corporation of America
InventorsLarry Phillips, Shuji Inoue, Edwin R. Meyer
Estimating the term…
A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value. The count value is compared to a succession of externally supplied system clock reference (SCR) values to generate a phase difference signal that is used to adjust the frequency of the signal produced by the DPLL. In addition, the DPLL is aligned in phase by substituting respective portions of the SCR value for the count value developed by the DPLL and for the accumulated phase value used by the DPLL.
Apparatus for decoding a data stream including a plurality of variable length encoded data values representing an image where the data stream represents video signals having luminance components and chrominance components, the apparatus comprising:
Apparatus for decoding a data stream including a plurality of variable length encoded data values representing an image where the data stream represents video signals having luminance components and chrominance components, the apparatus comprising:
A circuit for decoding video signals encoded according to the MPEG-2 standard, consisting essentially of:
A system which synchronizes an internally generated oscillatory signal to an externally supplied multi-bit phase reference signal comprising:
Dependencies are inferred from the claim text.