Column redundancy circuit and method of semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorChuroo Park
Life of this patent
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Abstract
A column redundancy circuit and method of a semiconductor memory device. The column redundancy circuit comprises a programming element for programming a repair column address; a comparing element for comparing the programmed repair column address with a column address inputted from outside to thereby generate a redundancy enable control signal according to result of the comparison; a decoding element for decoding the repair column address signal to thereby generate a decoding signal; and a redundancy column select element for compounding the decoding signal and a data input signal to thereby enable a redundancy column select signal.
Claims15
A semiconductor memory device that provides for substituting a normal memory cell with a defective memory cell, comprising:
- a column redundancy circuit including a program circuit that programs and stores a plurality of repair column address in a register, a comparison circuit that compares said repair column address stored in said register with a column address externally input, a decoder that operates to decode said repair column address and obtain decoded signals, and a redundancy column select circuit that operates in a block select mode to generate a column redundancy enable signal corresponding to data input from a data input buffer and said decoded signals.
A column redundancy circuit of a semiconductor memory device that provides for substituting a normal memory cell for a defective memory cell, comprising:
- programming means for programming a repair column address;
- comparing means for comparing said repair column address with an externally input column address to thereby generate a redundancy enable control signal according to this comparison;
- decoding means for decoding said repair column address signal to generate a decoding signal;
- and
- redundancy column select means for operating on said decoding signal and a data input signal in a block select mode to enable a redundancy column select signal.
A column redundancy method that provides for substituting a normal memory cell for a defective memory cell, said method comprising the steps of:
- programming a repair column address;
- storing said programmed repair column address in said register;
- comparing said stored repair column address with an externally input column address input and generating a redundancy enable control signal according to this;
- decoding said repair column address signal and generating a decoding signal;
- and
- operating on said decoding signal and a data input signal in a block select mode to enable a redundancy column select signal.
Dependencies are inferred from the claim text.