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US 5,621,675 AGranted
Digital decimation and compensation filter system
AssigneeAdvanced Micro Devices, Inc.
InventorsAlfredo R. Linz, Glen Brown
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Abstract
This invention is for a multi-stage digital decimation filter, which includes a sinc.sup.6 filter, a half-band linear phase FIR filter and a symmetric, linear phase, FIR filter and a digital compensation filter. The multi-stage decimation filter down-samples the output of a sigma-delta modulator by a factor of about 64. The compensation filter provides compensation for rolloff introduced by the multi-stage decimation filter.
Claims6
A digital decimation filter, comprising:
- a first decimator stage, which decimates by a factor of 16, having an input and an output, wherein said input is connected to a digital signal output from a sigma-delta modulator;
- a second decimator stage, which decimates by a factor of two, having an input and an output, wherein said input is connected to the output of said first decimator stage;
- and
- a third decimator stage, which decimates by a factor of two, having an input and an output, wherein said input is connected to the output of said second decimator stage and said output provides a multi-bit digital output signal;
- wherein a sample of a digital signal output from said first decimator stage output is input to said second decimator stage, wherein every other sample of said first decimator stage output signal is provided via a switch to a plurality of multipliers in said second stage wherein each said multiplier multiplies said every other sample by a respective decimator filter coefficient to produce a scaled sample value, and wherein some of said scaled sample values are applied to a plurality of summing nodes in said second stage, wherein an output of each said node is input to a respective corresponding delay block in said second stage, and wherein an other every other sample of said first decimator stage output is input to a filter center tap delay block in said second stage prior to being provided to said plurality of summing nodes.
2 more elements
A digital decimation filter, comprising:
- a first decimator stage, which decimates by a factor of 16, having an input and an output,wherein said input is connected to a digital signal output from a sigma-delta modulator;
- a second decimator stage, which decimates by a factor of two, having an input and an output, wherein said input is connected to the output of said first decimator stage;
- and
- a third decimator stage, which decimates by a factor of two, having an input and an output wherein said input is connected to the output of said second decimator stage and said output provides a multi-bit digital output signal;
- wherein in said third decimator stage a sample of said digital signal output from said second decimator stage output is provided simultaneously as an input signal sample to a plurality of multipliers in said third stage, wherein each said multiplier multiplies said sample by a respective decimator filter coefficient to produce a scaled sample value, and wherein some of said scaled sample values are applied to a plurality of summing nodes in said third stage, wherein an output of each said node is input to a respective corresponding delay block in said third stage, and wherein an other every other sample of said second decimator stage output is input to a filter center tap delay block in said third stage prior to being provided to said plurality of summing nodes.
2 more elements
A digital decimation and attenuation compensation system, comprising:
- a first decimator stage, which decimates by a factor of 16, having an input and an output, wherein said input is connected to a digital signal output from a sigma-delta modulator;
- a second decimator stage, which decimates by a factor of two, having an input and an output, wherein said input is connected to the output of said first decimator stage;
- a third decimator stage, which decimates by a factor of two, having an input and an output, wherein said input is connected to the output of said second decimator stage and said output provides a multi-bit digital output signal;
- and
- a digital compensation filter, wherein said filter comprises a Nyquist rate FIR compensation filter, having an input and an output, wherein said compensation filter input is connected to said multi-bit digital output signal of said third decimator stage, and wherein said compensation filter increases the amplitude of a signal output from said third decimator stage to compensate for frequency rolloff introduced by said first, second or third decimator stage, and wherein said output of said digital compensation filter provides a multi-bit digital output signal.
2 more elements
Dependencies are inferred from the claim text.