Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture

An apparatus, comprising:

• a first memory;
• a second memory;
• a processor;
• means for translating a sequence of instructions of a first semantic type stored in the first memory into one or more instructions of a second semantic type and for storing the instructions of the second type in the second memory;
• means, upon a request from the processor for the sequence of instructions of the first semantic type:
• for providing the corresponding instructions of the second semantic type if available in the second memory;
• and
• for providing the sequence of instructions of the first semantic type if the corresponding instructions of the second semantic type are not available in the second memory.

An apparatus, comprising:

• a main memory;
• an instruction cache memory coupled to the main memory via a first bus;
• a processor coupled to the instruction cache memory via a second bus;
• an address bus connecting the processor and the instruction cache memory for delivering instruction request signals from the processor to the instruction cache;
• means responsive to the instruction request signals for transferring requested instructions from the instruction cache memory to the processor if the requested instructions are stored in the instruction cache memory;
• means responsive to the instruction request signal for transferring the requested instructions from the main memory to the processor via the instruction cache memory if the requested instructions are not stored in the instruction cache memory;
• a translation engine coupled to receive instructions output from the instruction cache memory via the second bus;
• a storage unit coupled to receive translated instructions corresponding to the requested instructions from the translation engine;
• means responsive to the instruction request signal for transferring the translated instructions stored in the storage unit to the processor.

An apparatus, comprising:

• a main memory;
• an instruction cache memory coupled to receive outputs from the main memory;
• a translation engine coupled to receive outputs from the main memory;
• an extended instruction cache coupled to receive outputs from the translation engine;
• a processor coupled to receive outputs from the instruction cache and from the extended instruction cache;
• means for delivering instruction request signals from the processor to the instruction cache and to the extended instruction cache;
• means for translating a plurality of instructions, conveyed to the translation engine via the second bus, into one or more primary instructions;
• means for storing the plurality of instructions in the instruction cache;
• means responsive to the instruction request signal for conveying the one or more primary instructions to the processor, if the primary instructions exist;
• means responsive to the instruction request signal for conveying the plurality of instructions from the instruction cache memory to the processor if no primary instruction corresponding to the plurality of instructions exists.