Multiple step method of chemical-mechanical polishing which minimizes dishing

A semiconductor processing method of minimizing chemical-mechanical polishing dishing in the formation of a planar outer surface having an electrically conductive area adjacent an insulating dielectric area on a semiconductor wafer, the method comprising the following steps:

• providing a trough in a dielectric layer and thereby defining a non-planar wafer topography;
• providing a conformal blanketing layer of a conductive material over the dielectric layer and within the trough;
• providing a chemical-mechanical polishing protective layer over the conformal layer of conductive material, the protective layer being of different composition than the conformal conductive layer;
• and
• chemical-mechanical polishing the protective layer and conformal conductive layer in at least two chemical-mechanical polishing steps using first and second respective chemical-mechanical polishing slurries, the first chemical-mechanical polishing step and slurry removing outermost portions of the protective layer from said troughs in a manner which is substantially selective to the underlying conformal conductive layer to outwardly expose conformal conductive layer material in high topographical areas, the second chemical-mechanical polishing step and slurry removing the conformal conductive layer material at a faster rate than the protective layer material, the protective layer upon outward exposure of conformal conductive layer material in high topographical areas restricting material removal from low topographical areas during such second chemical-mechanical polishing step and thereby minimizing dishing of the conductive material within the trough.