Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor

A method for internally testing a plurality of embedded memories of a data processor, wherein at least two of the plurality of embedded memories are different in that one embedded memory contains N memory locations and the other embedded memory contains M memory locations wherein N.noteq.M, the data processor and the plurality of embedded memories being formed together in one integrated circuit, the method comprising the steps of:

• a) generating, by an internal test controller of the data processor, a first test pattern in a set of test patterns for the plurality of embedded memories, the generating being performed by intercoupled counters and state machines within the internal test controller, the intercoupled counters and state machines generating both test data in the first test pattern and address data in the first test pattern, the address data being used to determine which memory in the plurality of embedded memories is to be tested;
• b) transmitting the test data within the first test pattern of the set of test patterns via at least one bus of the data processor to a first embedded memory of the plurality of embedded memories identified by the address data of the first test pattern, the at least one bus being totally internal to the one integrated circuit and being electrically isolated from external to the one integrated circuit;
• c) storing the data portion of the first test pattern within predetermined cells of the first embedded memory;
• d) reading, by the internal test controller, the data portion from the predetermined cells of the first embedded memory via the at least one bus;
• e) updating, by the internal test controller, a signature value which indicates an integrity of the first embedded memory with respect to the first test pattern, the signature value having an output and an input wherein the output logically affects the input via a feedback connection between the input and the output;
• f) repeating steps (a) through (e) with the first embedded memory for remaining test patterns of the set of test patterns;
• g) repeating steps (b) through (f) for remaining embedded memories of the plurality of memories;
• h) providing an output in response to a final signature value which indicates whether the plurality of embedded memories are functioning properly.

An internal test controller of a data processor wherein the data processor includes a plurality of embedded memories, each of the data processor, the internal test controller, and the embedded memories are formed together in a single integrated circuit, the internal test controller comprising:

• a test pattern generator that generates a test pattern for each embedded memory within the plurality of embedded memories and sequentially provides the test pattern to each embedded memory of the plurality of embedded memories via a bus internal to the single integrated circuit;
• and
• a memory verification element that is operably coupled to the test pattern generator via the bus internal to the single integrated circuit, the bus being used to conduct information from the test pattern generator and conduct information to the memory verification element in a time multiplexed manner, wherein the memory verification element verifies correct operation of the plurality of embedded memories by reading memory data from each embedded memory after writing the test pattern to the plurality of embedded memories, the memory data being provided to a storage element that changes from a first state to a second state in response to the memory data and the first state within the storage element, the storage element providing a signal that indicates whether the plurality of embedded memories are operating properly.

An data processor having a plurality of embedded memories, the data processor comprising:

• an internal test controller, the internal test controller comprising:
• a test pattern generator that generates a test pattern for the plurality of embedded memories and sequentially selects each embedded memory of the plurality of embedded memories;
• and
• a memory verification element that is operably coupled to the test pattern generator, wherein the memory verification element verifies integrity of the plurality of embedded memories based on results of memory testing the plurality of embedded memories using the test pattern;
• a first storage device for storing data being read from each embedded memory within the plurality of embedded memories;
• a second storage device for storing at least a portion of the test pattern from the internal test controller;
• and
• a bi-directional bus coupled among the first storage device, the second storage devices, the memory verification element, and the test pattern generator, the bi-directional bus being internal to the data processor, the bi-directional bus allowing data within the first storage device to be selectively communicated to the memory verification element, and allowing the at least a portion of the test pattern to be selectively stored within the second storage device in a time-multiplexed manner.

An integrated circuit wafer comprising:

• a plurality of integrated circuit chips wherein each of the chips in the plurality of integrated circuit chips has one built-in self-test controller for testing a plurality of memories on each of the integrated circuit chips;
• a conductive metallic clock interconnect coupled across the integrated circuit wafer to each integrated circuit chip in the plurality of integrated circuit chips, the integrated circuit wafer requiring at least one signal via the conductive metallic clock interconnect to invoke wafer-level integrated circuit testing and requiring a clock signal to each integrated circuit die to perform wafer-level integrated circuit testing, each of the chips in the plurality of integrated circuit chips providing at least one output signal from a signature analyzer to identify which integrated circuits passed testing and which integrated circuits failed testing;
• and
• conductive elements coupled to the at least one output signal of each integrated circuit chip in the plurality of integrated circuit chips to detect which integrated circuits passed testing and which integrated circuits failed testing.

A method for internally testing a plurality of embedded memories of a data processor, wherein the data processor is formed on a single integrated circuit and at least two of the plurality of embedded memories are different in physical placement within the single integrated circuit, the method comprising the steps of:

• generating, by an internal test controller of the data processor, a test pattern for testing the plurality of embedded memories, the test pattern having a plurality of bits;
• transmitting the plurality of bits of the test pattern in a parallel manner via at least one bus of the data processor to one embedded memory in the plurality of embedded memories, the transmitting being performed by a bus totally internal to the single integrated circuit;
• reading, by the internal test controller, the at least a portion of the test pattern from the predetermined cells of the one embedded memory, the reading being performed by the bus totally internal to the single integrated circuit, wherein the step of reading is time multiplexed from the step of writing;
• storing at least a portion of the test pattern within predetermined cells of the one embedded memory;
• and
• verifying, by the internal test controller via the steps of reading and storing, that the one embedded memory is functioning properly, the verifying being performed by storing data in a verification storage element wherein the storage element is a signature analyzer having a feedback path from an output to an input of the signature analyzer.

A method for internally testing memories which are coupled to a CPU within an integrated circuit, the method comprising the steps of:

• (a) generating a test pattern and a memory test address internal to the integrated circuit using a set of intercoupled state machines and counters;
• (b) applying the test pattern to each memory location in a selected memory within the integrated circuit, the selected memory being identified via the memory test address;
• (c) reading contents of the selected memory written to in step (b);
• (d) processing the contents internal to the integrated circuit to determine an integrity data value where the integrity data value is a function of all past contents read from the selected memory;
• (e) generating a different test pattern to use as the test pattern and repeating steps (b) through (e) wherein the repeating of steps (b) through (e) is performed until all of a plurality of predetermined test patterns are exhausted;
• and
• (f) selecting a new selected memory that has not been tested and repeating steps (a) through (f) until all memories have been tested.

A method for internally testing memories which are coupled to a CPU within an integrated circuit, the method comprising the steps of:

• (a) generating a test pattern and address internal to the integrated circuit;
• (b) applying the test pattern to each memory location in each memory within the integrated circuit;
• (c) reading contents of the each memory;
• (d) processing the contents via a signature analyzer internal to the integrated circuit to determine an integrity data value where the integrity data value is a function of all past contents read from the memories due to a feedback path from an output of the signature analyzer to an input of the signature analyzer;
• and
• (e) generating a different test pattern to use as the test pattern and repeating steps (a) through (e) wherein the repeating of steps (a) through (e) is performed until all of a plurality of predetermined test patterns are exhausted.