Digital signal processing for linearization of small input signals to a tri-state power switch

Abstract

An all digital switching amplifier wherein linearization of the power switch is accomplished solely by using three states. A small, fixed width, bi-state compensating carrier waveform is added to the leading or training edges of an oversampled main input pulse producing a compensated composite waveform. This compensating carrier linearizes output from a power switch by effecting common mode cancellation of switch time errors. Output pulse width combinations for the compensating carrier are obtained from a look-up table stored in memory. A correction mechanism is implemented to correct for harmonic distortion that is dependent on the modulation level or index and results from the compensating carrier modulation. The correction mechanism applies the inverse of the modulation induced distortion to the oversampled compensated composite input signal to null distortion products resulting from the modulation scheme used to apply the small carrier to linearize the performance of the tri-state power switch. Digital timing control of the power switch's deadband ensures accuracy of the timing and sequence in which individual switches within the power switch H-bridge are turned off and turned on, so as to preclude a short circuit across the power supply. A high speed clock used in linearizing the power switch provides a timing reference to generate the necessary deadband timing delays and pulse width increments. The output bridge uses enhancement mode MOSFETs.

Dependencies are inferred from the claim text.