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US 5,615,358 AGranted
Time skewing arrangement for operating memory in synchronism with a data processor
AssigneeTexas Instruments Incorporated
InventorWilbur C. Vogley
Life of this patent
Estimating the term…
Abstract
A data processing system includes a plurality of synchronous random access memory devices, a data processor, and a time skewing circuit interposed between the data processor and the plurality of synchronous memory devices. The time skewing circuit imparts different increments of delay time into memory clock and address signals transmitted to different ones of the synchronous memory devices, imparts different increments of delay time into various control signals, and imparts a uniform increment of delay time into several write enable signals. The read enable signals and the write enable signals are used for loading data into data storage devices, which are a part of the time skewing circuit that is interposed between the data processor and the synchronous memory devices.
Claims14
A data processing system comprising:
- a plurality of synchronous random access memory devices, each memory device including at least one array of memory cells;
- a digital processor for producing address signals, data signals, and control signals to be transmitted to the plurality of memory devices and for receiving data signals read from the plurality of memory devices;
- and
- a time skewing circuit, interposed between the digital processor and the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous random access memory devices, for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the memory devices.
1 more element
An electrical circuit module comprising:
- a circuit board;
- a plurality of synchronous random access memory devices, each memory device including at least one array of memory cells and being fixed to the circuit board;
- a time skewing circuit, fixed to the circuit board and interconnected with the plurality of memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the memory devices, for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data into the data storage devices of the time skewing circuit.
An electrical circuit module comprising:
- a circuit board;
- a plurality of synchronous memory devices fixed to the circuit board;
- a time skewing circuit fixed to the circuit board;
- an address bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices;
- a data bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices;
- a clock bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices;
- and
- a control bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of memory devices.
5 more elements
A data processing system comprising:
- a plurality of synchronous memory devices, each memory device including at least one array of memory cells;
- a digital processor for producing address signals, data signals, and control signals to be transmitted to the plurality of synchronous memory devices and for receiving data signals read from the plurality of synchronous memory devices;
- and
- a time skewing circuit, interposed between the digital processor and the plurality of synchronous memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous memory devices, for imparting different increments of delay time into read enable signals, for loading data read from the synchronous memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data from the digital processor into the data storage devices of the time skewing circuit for subsequent writing into the synchronous memory devices.
1 more element
An electrical circuit module comprising:
- a circuit board;
- a plurality of synchronous memory devices, each memory device including at least one array of memory cells and being fixed to the circuit board;
- a time skewing circuit, fixed to the circuit board and interconnected with the plurality of synchronous memory devices for imparting different increments of delay time into memory clock signals transmitted to different ones of the synchronous memory devices, for imparting different increments of delay time into read enable signals for loading data read from the memory devices into data storage devices included within the time skewing circuit, and for imparting a uniform increment of delay time into write enable signals for loading data into the data storage devices of the time skewing circuit.
An electrical circuit module comprising:
- a circuit board;
- a plurality of synchronous memory devices fixed to the circuit board;
- a time skewing circuit fixed to the circuit board;
- an address bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices;
- a data bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices;
- a clock bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices;
- and
- a control bus, fixed to the circuit board and interconnecting the time skewing circuit with the plurality of synchronous memory devices.
5 more elements
Dependencies are inferred from the claim text.