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US 5,615,159 AGranted
Memory system with non-volatile data storage unit and method of initializing same
AssigneeMicron Quantum Devices, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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AssigneeMicron Quantum Devices, Inc.
InventorFrankie F. Roohparvar
Estimating the term…
A memory system (preferably implemented as an integrated circuit) including an array of memory cells, a control unit for controlling operations of the system (such as programming, reading, and erasing the cells), at least one data storage unit which stores control parameter data determining at least one control parameter for the system, and default parameter circuitry for asserting at desired times one or both of: default control parameter data (regardless of the control parameter data stored in each data storage unit); and at least one default voltage level (in place of an otherwise asserted voltage level). In preferred embodiments, the default control parameter data (or voltage levels) are asserted during a test initialize mode in response to an initialization signal generated by the control unit, for use in initializing internal control registers (and voltage levels) of the system so that an external program for controlling the system during the test mode can start from a known condition. Other embodiments are methods for asserting default control parameter data of memory systems at desired times during system operation (regardless of the values of control parameter data stored in storage units of the system), methods for asserting default voltage values at desired times during operation of such systems, and memory systems capable of performing such methods.
A memory system, including:
A memory system, including:
A method for operating a memory system in a test mode, said system including a data storage unit and a memory means capable of operating in a normal operating mode under control of signals including a parameter signal indicative of control parameter data stored in the data storage unit, said method including the steps of:
A method for operating a memory system in a test mode, said system including a memory means capable of operating in a normal operating mode in which a reference voltage is asserted at a first node, said method including the steps of:
Dependencies are inferred from the claim text.