US 5,613,146 AGranted

Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors

AssigneeTexas Instruments Incorporated

InventorsRobert J. Gove, Keith Balmer, Nicholas K. Ing-Simmons, Karl M. Guttag

Life of this patent

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Abstract

There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and an inter-processor communication link allows the processors to communicate with each other for the purpose of establishing operational modes. A parameter memory, accessible via the crossbar switch, is used in conjunction with the communication link for control purposes. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Claims7

Dependent claims

A multi-processor system operating in a selected one of a plurality of modes comprising:

a plurality of processors, each processor having a data port and a separate instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;
a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors and at least one parameter memory;
a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said data port of each of said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, said switch matrix further connecting said instruction port of each processor to said corresponding instruction memory, said switch matrix connecting any of said plurality of processors for access to said at least one parameter memory regardless of said operational mode;
and
an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode, said interprocessor communication bus transmitting a parameter read signal from any processor to any other selected processor to read data stored in said at least one parameter memory.

2 more elements

A multi-processor system operating in a selected one of a plurality of modes comprising:

a plurality of processors, each processor having a data port and an instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;
a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors;
a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, one of said operational modes of said switch matrix being a multiple instruction multiple data mode, said switch matrix connecting processors to memory in said multiple instruction multiple data mode whereby:
each of said processors accesses instructions via said instruction port and said switch matrix from said corresponding instruction memory for supply via said switch matrix to said instruction port of said processor, and
each of said processors accesses data via said data port and said switch matrix within any of said plurality of memories except said instruction memories;
and
an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode.

4 more elements

A multi-processor system operating in a selected one of a plurality of modes comprising:

a plurality of processors, each processor having a data port and a separate instruction port and operating from instructions provided to said instruction port for controlling a process including movement of data to and from said data port;
a plurality of memories greater in number than the number of said plurality of processors, said plurality of memories including an instruction memory corresponding to each of said processors;
a switch matrix connected to said data port and said instruction port of each of said plurality of processors and each of said plurality of memories, said switch matrix for selectively and concurrently connecting said processors and said memories in a plurality of operational modes, each of said operational modes including only predetermined particular processor to memory accesses, one of said operational modes of said switch matrix is a concurrent single instruction multiple data and multiple instruction multiple data mode wherein a first subset of said plurality of processors operate in said single instruction multiple data mode and a second subset of said plurality of processors operate in said multiple instruction multiple data mode, said switch matrix connecting processors to memory in said concurrent single instruction multiple data and multiple instruction multiple data mode whereby:
a predetermined one of said processors of said first subset of processors accesses instructions via said instruction port and said switch matrix from said corresponding instruction memory for supply via said switch matrix to said instruction port of each of said processors of said first subset of processors,
each of said processors of said second subset of processors accesses instructions via said instruction port and said switch matrix from said corresponding instruction memory for supply via said switch matrix to said instruction port of said processor, and
each of said processors accesses data via said data port and said switch matrix within any of said plurality of memories except said instruction memory corresponding to said predetermined one of said processors of said first subset of processors and said instruction memories corresponding to said processors of said second subset of processors;
and
an interprocessor communication bus connected to each of said processors for transmitting signals from any processor to any other selected processor for effecting changes in said operational mode.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/483,658Filed 7 Jun 1995 · continuation
Priority: 17 Nov 1989
Granted: 18 Mar 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 15/8015
Single instruction multiple data [SIMD] multiprocessors: one dimensional arrays, e.g. rings, linear arrays, buses
G06F 15/17375
Non hierarchical topologies: one dimensional, e.g. linear array, ring
G06F
Computing and data processing

Family

Serial437,856Parent of this continuation · filed 17 Nov 1989
Serial895,565Parent of this continuation · filed 5 Jun 1992
Serial264,111Parent of this continuation · filed 22 Jun 1994
US 5,522,083 AParent of this continuation
US 5,613,146 AThis patent

From the US filing history. Foreign family members aren’t listed.