Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller

A multi-processor programmable interrupt controller system, comprising:

• (a) a common system bus;
• (b) an interrupt bus;
• (c) at least one I/O interrupt controller, coupled to said interrupt bus, operable to receive an interrupt, request signal and, responsive thereto, to transmit formatted interrupt requests on said, interrupt bus;
• (d) a multiplicity of processors, coupled to said common system bus, each comprising a central processor unit with data, address, and control ports;
• and
• (e) a multiplicity of local processor interrupt controllers, each coupled to said data, address, and control ports of an associated one of said processors and each coupled to said interrupt bus, each being operable to receive said formatted interrupt requests from said interrupt bus and to accept those which said associated processor is eligible to service, to broadcast on said interrupt bus an acceptance signal upon said acceptance, to queue said accepted interrupt requests, to deliver in priority order said accepted interrupts to said associated processor for servicing, and to generate a priority arbitration sequence for arbitrating between eligible candidate processors, said priority arbitration sequence comprising:
• (i) a priority sequence based on the current priority of each processor;
• and
• (ii) a unique randomized arbitration identifying sequence for determining the winning lowest priority processor.

A local processor interrupt controller for a multi-processor system, comprising:

• (a) send/receive means for receiving and sending interrupt and arbitration related messages on an interrupt bus;
• (b) acceptance logic means for rejecting, accepting, and arbitrating received interrupt request messages;
• (c) recording means, coupled to the acceptance logic means and to the send/receive means, for recording the status of accepted interrupt request messages including interrupt type and priority information;
• (d) nesting storage means for priority ordering of the accepted interrupt requests, coupled to the local processor data and address ports, for storing and delivering the highest priority interrupt request when its associated local processor's priority is less than the highest priority queued interrupt request, and for sending a delivery attempt accepted acknowledgment from the processor to the sending source on the interrupt bus;
• (e) means for storing the local processor interrupt controller identification number, coupled to the associated processor data and address ports for assignment of a processor programmable identification number, and coupled to the send/receive means and to the acceptance logic means for arbitrating and accepting received interrupt request signals;
• and
• (f) means for tracking the associated processor's current task priority and delivering the task priority to the acceptance logic means for arbitrating and accepting received interrupt request signals.

A multi-processor programmable interrupt controller system for operation in a multi-processor environment that comprises a multiplicity of processors and at least one peripheral unit interconnected by a common system bus, comprising:

• (a) an interrupt bus means, distinct from said common system, bus for communicating an interrupt request message;
• (b) an I/O controller means, coupled to said interrupt bus means and at least one associated peripheral unit, for accepting an interrupt signal from said peripheral unit, for formatting said interrupt signal for transmission on said interrupt bus means, said formatted interrupt signal being representative of the nature and priority of said interrupt signal and of the group of processors eligible to service said interrupt signal, and for transmitting said formatted interrupt signal on said interrupt bus means;
• (c) a multiplicity of local processor controller means, coupled to said interrupt bus means, each local processor controller means being associated with a specific processor, for receiving and accepting said formatted interrupt signals which said associated processor is eligible to service, for broadcasting on said interrupt bus an acceptance of said formatted interrupt signals, for queuing said interrupt signals that are accepted, and for delivering said interrupt signals that are accepted to said associated processor for servicing;
• (d) priority acceptance means for arbitrating the acceptance of interrupt signals based on the current priority of the associated local processor task so that, amongst the eligible processors, the local processor controller associated with the lowest priority processor accepts the interrupt request signal;
• and
• (e) arbitration acceptance means for selecting one of the local processors included in a subset of eligible processors operating at the same lowest level priority so as to distribute the request and servicing with uniform probability amongst the subset of eligible processors operating at the same lowest priority level.