Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions

A computer system comprising:

• means for issuing instructions, some of which are speculative instructions, each of said instructions specifying a virtual address;
• translation lookaside buffer means for storing physical addresses corresponding to selected virtual addresses;
• page miss handler means for determining the physical address corresponding to a virtual address for virtual addresses not stored within said translation lookaside buffer means;
• memory ordering buffer means for reordering and blocking memory instructions;
• blocking means, operative in response to a translation lookaside buffer means miss, for determining whether the page miss handler means is busy and for controlling the memory ordering buffer means to block an instruction causing the translation lookaside buffer miss until the page miss handler means is no longer busy;
• and
• wake up means for awakening instructions blocked by the blocking means and for transmitting the awakened instructions to the translation lookaside buffer means.

A computer system comprising:

• an instruction fetch and issue unit to issue instructions, some of which are speculative instructions, each of said instructions specifying a virtual address;
• a translation lookaside buffer to store physical addresses corresponding to selected virtual addresses;
• a page miss handler to determine the physical address corresponding to an instruction for addresses not stored within said translation lookaside buffer;
• a memory ordering buffer to reorder and block memory instructions;
• a blocking unit, operative in response to a translation lookaside buffer miss to determine whether the page miss handler means is busy and to control the memory ordering buffer to block an instruction causing the translation lookaside buffer miss until the page miss handler is no longer busy;
• and
• a wake up unit to awaken instructions blocked by the blocking unit and to transmit the awakened instructions to the translation lookaside buffer.

A computer system comprising:

• a plurality of microprocessors each having
• an instruction fetch and issue unit to issue instructions, some of which are speculative instructions, each of said instructions specifying a virtual address;
• a translation lookaside buffer to store physical addresses corresponding to selected virtual addresses;
• a page miss handler to determine the physical address corresponding to the virtual address of an instruction not stored within said translation lookaside buffer;
• a memory ordering buffer for reordering and blocking memory instructions;
• a blocking unit, operative in response to a translation lookaside buffer miss, to determine whether the page miss handler is busy and to control the memory ordering buffer to block an instruction causing the translation lookaside buffer miss until the page miss handler is no longer busy;
• a wake up unit to awaken instructions blocked by the blocking unit and to transmit the awakened instructions to the translation lookaside buffer;
• a memory;
• an input/output unit;
• and
• a system bus interconnecting said microprocessors, said memory and said input/output unit.

A microprocessor comprising:

• an instruction fetch and issue unit configured to issue instructions, wherein some of said instructions are speculative instructions and each of said instructions specifying a virtual address;
• a translation lookaside buffer configured to store physical addresses corresponding to selected virtual addresses;
• a page miss handler configured to determine the physical address corresponding to an instruction for addresses not stored within said translation lookaside buffer;
• a memory ordering buffer configured to reorder and block memory instructions;
• a blocking unit, operative in response to a translation lookaside buffer miss, to determine whether the page miss handler is busy and to control the memory ordering buffer to block an instruction causing the translation lookaside buffer miss until the page miss handler is no longer busy;
• and
• a wake up unit for awakening instructions blocked by the blocking unit and for transmitting the awakened instructions to the translation lookaside buffer.