High performance, fault tolerant orthogonal shuffle memory and method

A method for sequentially accessing, storing, reading and writing data in a memory comprising first and second multi-stage registers holding one data bit per stage and a memory cell array coupled to said first and second registers and having rows and columns of memory cells, each memory cell from said memory cell array including a data storage element and a data transmission element coupled to said data storage element, said method comprising the steps of:

• (a) transferring the data contents of the data storage elements of the first column of memory cells of said array into the first register during a first time interval by way of respective ones of said data transmission elements of said first column of memory cells;
• (b) transferring the data contents of the data storage elements of the second column of memory cells of said array into the data storage elements of the memory cells of said first column during a second time interval by way of respective ones of said data transmission elements of said second column of memory cells;
• (c) transferring the data contents of the data storage elements of each succeeding column of memory cells of said array into the data storage elements of the memory cells of the immediately-preceding column during another time interval by way of respective ones of said data transmission elements of said succeeding column of memory cells;
• (d) repeating step (c) until the data contents of the data storage elements of the last column of memory cells of said array are transferred into the data storage elements of the memory cells in the next-to-last column by way of respective ones of said data storage elements of said last column of memory cells, such that data is transferred between the storage elements of the memory cells of only two columns of said array during any time interval;
• (e) transferring the data contents of said second register into the data storage elements of the last column of memory cells of said array;
• (f) shifting the data contents of said first and second registers by one bit during each of said steps (a) through (e);
• and
• (g) supplying the data contents of the first stage of said first register into the first stage of said second register during each of said steps (a) through (e).