Multi-bank synchronous memory system with cascade-type memory cell structure

A synchronous memory system with a cascade-type memory cell structure for receiving address signals for a memory cell to be accessed and reading out of data stored in the memory cell being performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising:

• a plurality of bit lines;
• a plurality of memory cells having a cascade-type configuration connected to each of the plurality of bit lines;
• a plurality of word lines connected to the plurality of memory cells;
• and
• a row decoder comprising:
• a plurality of first decode circuits for receiving a first row address signal and decoding the first row address signal and generating a first drive control signal, each first decode circuit comprising a first PMOS precharging transistor and first NMOS discharging transistors connected in series;
• a plurality of word line drive units for receiving the first drive control signal and providing a first drive signal to the plurality of word lines, each first drive unit having a first NMOS transistor and a second NMOS transistor connected in series, an intermediate node between the first NMOS transistor and the second NMOS transistor belonging to one the plurality of word lines;
• a plurality of first flip/flop circuits (F/Fs) for storing the first drive control signal, each first F/F being located between each first decode circuit and each word line drive unit, each first F/F comprising second and third inverters connected in series, each first F/F being driven by the first voltage;
• a plurality of fourth inverters, each fourth inverter placed between each first F/F and each word line drive unit, each fourth inverter driven by the first voltage;
• and
• a voltage generation circuit for receiving a first voltage and a second row address signal, and generating second drive signals and providing the second drive signals to the first NMOS transistor of each of the plurality of word line drive units according to the second row address signal.

A synchronous memory system with a cascade-type memory cell structure for receiving address signals for a memory cell to be accessed and reading out of data stored in the memory cell being performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising:

• a plurality of bit lines;
• a plurality of memory cells having a cascade-type configuration connected to each of the plurality of bit lines;
• a plurality of word lines connected to the plurality of memory cells;
• and
• a row decoder comprising:
• a plurality of first decode circuits for receiving a first row address signal and decoding the first row address signal and generating a first drive control signal, each first decode circuit comprising a first PMOS precharging transistor and first NMOS discharging transistors connected in series;
• a plurality of first flip/flop circuits (F/Fs) for storing the first drive control signal, each first F/F being located between each first decode circuit and each word line drive unit, each first F/F comprising second and third inverters connected in series;
• a plurality of fourth inverters, each fourth inverter placed between each first F/F and each word line drive unit;
• and
• a plurality of word line drive units for receiving the first drive control signal and providing a first drive signal to the plurality of word lines, each first drive unit having a first PMOS transistor and a first NMOS transistor connected in series, an intermediate node between the first PMOS transistor and the first NMOS transistor belonging to one the plurality of word lines;
• and
• a voltage generation circuit for receiving a first voltage and a second row address signal, generating second drive signals and providing the second drive signals to the first PMOS transistor of each of the plurality of word line drive units according to the second row address signal, and boosting up the first voltage to a second voltage,
• wherein the first PMOS precharging transistor in each first decode circuit, the second and third inverters in each first F/F, each fourth inverter are driven by the second voltage.

A synchronous memory system with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell being performed in synchronization with a first clock signal supplied externally, the synchronous memory system comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of first memory cells having a cascade-type configuration connected to the plurality of word lines, the plurality of first memory cells forming a memory cell group in a plurality of memory cell groups in a memory cell array, the memory cell group being connected to one of the plurality of bit lines;
• a plurality of transfer gates provided to each of the plurality of the bit lines to connect each memory cell group to each of the plurality of the bit lines;
• a sense amplifier connected to each of the plurality of bit lines for sensing data to be written into each of the plurality of first memory cells or for sensing data to be read out from each of the plurality of first memory cells;
• an equalizer provided for the sense amplifier for equalizing a voltage potential of each of the plurality of bit lines;
• a plurality of second memory cells located between the plurality of first memory cells and the sense amplifier, the plurality of second memory cells provided for the plurality of first memory cells;
• a selector for receiving an address signal of a target memory cell to be accessed in the plurality of first memory cells according to the first clock signal,
• selecting each of the plurality of first memory cells while saving data of the selected each of the plurality of first memory cells to the plurality of second memory cells in synchronism with the first clock signal and counting a number of the selected each of the plurality of first memory cells,
• generating a sense operation halt control signal when the target memory cell being selected and whose data being stored to the sense amplifier, and transmitting the sense operation halt control signal externally;
• and
• a decoder for receiving the address signal of the target memory cell and generates access control signals for controlling operations of the plurality of first memory cells, the plurality of transfer gates, the sense amplifier, the equalizer, and the plurality of second memory cells, and transmits the address control signals to the plurality of word lines, the plurality of transfer gates, the plurality of second memory cells, and the sense amplifier,
• wherein
• when a memory cell in the plurality of first memory cells in another memory cell group connected is a target memory cell to be accessed in series, a sense operation for the first memory cells including the target memory cell in another memory cell group is executed after the data items temporarily have been saved into the plurality of second memory cells are restored into corresponding the plurality of first memory cells including the preceding target memory cell.