Method of finding a critical path in a circuit by considering the clock skew

Abstract

The present invention is directed to a method of designing and fabricating a circuit layout which revolutionizes the manner by which critical weights of a circuit layout are assessed. In accordance with exemplary embodiments, a critical path is assessed on the basis of both a physical delay associated with a data propagation path and with respect to any clock skew which exists with respect to the data propagation path. A critical path can be a path having the shortest physical length from an input node to an output node if the clock skew along this path results in a high probability of a race condition. In accordance with exemplary embodiments, clock skew is assessed by determining the time differential between the arrival of a clock signal at a given data source instance and the arrival of a clock signal at a given data destination instance.

Dependencies are inferred from the claim text.