Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits
AssigneeAdvanced Micro Devices, Inc.
InventorsYowjuang W. Liu, Kuang-Yeh Chang
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Abstract
A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.
Claims18
A semiconductor device, comprising:
- a substrate of a first conductivity-type;
- a first active region and a second active region, each coupled to said substrate and having a second conductivity-type, said active regions separated from each other by a channel region;
- a well region having said second conductivity-type separated from said active regions;
- and
- a first buried region of said second conductivity-type, underlying said channel region and electrically coupled to said well region, for controlling a conductivity of said channel region.
A transistor, comprising:
- a substrate of a first conductivity-type;
- a first active region and a second active region, each coupled to said substrate and having a second conductivity-type, said active regions separated from each other by a channel region and providing a source and a drain of the transistor;
- a gate, disposed overlying said channel region, for controlling a conductivity of carriers in said channel region;
- a well region, having said second conductivity-type, separated from said active regions by an isolation region;
- and
- a first buried region of said second conductivity-type, underlying said channel region, said active regions and said isolation region, said first buried region electrically coupled to said well region, for controlling a conductivity of said channel region responsive to a voltage reference applied to said well region.
A semiconductor device, comprising:
- a substrate of a first conductivity-type;
- a first channel region, including:
- a first active region and a second active region, each coupled to said substrate and having a second conductivity-type, said first and second active regions separated from each other by a first channel region;
- a first well region having said second conductivity-type separated from said first and second active regions;
- a first buried region of said second conductivity-type, underlying said channel region and electrically coupled to said well region, for controlling a conductivity of said first channel region;
- and
- a second buried region of said first conductivity type, underlying said channel region and extending into said first well region;
- and
- a second channel region, including:
- a third active region and a fourth active region, each coupled to a second well region in said substrate and having said first conductivity-type, said third and fourth active regions in said second well separated from each other by a second channel region wherein said second well region has said second conductivity type;
- a fifth active region disposed in said second well region, having said second conductivity-type, said fifth active region separated from said third and fourth active regions in said second well region;
- a third buried region of said second conductivity-type, underlying said active regions in said second well region and extending across a width of said second well region, and
- a fourth buried region of said first conductivity-type, underlying said active regions in said second well region and extending across a width of said second well region,
- wherein said third and said fourth buried regions define a retrograde profile for said second well region.
Dependencies are inferred from the claim text.