Volatile memory cell with interface charge traps
AssigneeSGS-Thomson Microelectronics S.A.
InventorAlexander Kalnitsky
Life of this patent
Estimating the term…
Abstract
A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.
Claims16
A volatile memory cell comprising an insulated gate field effect transistor with charge traps in an insulating layer, wherein substantially all of said charge traps are located within approximately 1.0 nm of an interface between a semiconductor layer and the insulating layer.
A semiconductor device comprising:
- a semiconductor layer;
- an insulating layer disposed on the semiconductor layer defining an interface between the semiconductor layer and the insulating layer;
- charge traps located in the insulating layer, said charge traps for retaining charge;
- wherein substantially all of the charge traps are located within approximately 1.0 nm from the interface.
A memory device comprising:
- a semiconductor layer;
- an insulating layer disposed on the semiconductor layer defining an interface between the semiconductor layer and the insulating layer;
- charge traps located in the insulating layer;
- wherein substantially all of said charge traps are located within 1.0 nm of the interface.
A memory device comprising:
- an insulated gate field effect transistor including an insulating layer having a common interface with a semiconductor substrate, charge traps located in the insulating layer, said charge traps for retaining charge,
- wherein substantially all of said charge traps are located within approximately 1.0 nm of said common interface, and
- wherein said retained charge modulates a threshold of the transistor.
A memory device comprising:
- an insulated gate field effect transistor including an insulating layer disposed on a semiconductor substrate;
- charge traps located in the insulating layer, said charge traps for retaining charge for a finite period of time;
- said retained charge modulating a threshold of the transistor;
- wherein substantially all of the charge traps are located within approximately 1.0 nm of an interface between the insulating layer and the substrate;
- and
- wherein the finite period of time is a function of a density of the charge traps in the insulating layer and the distance to the interface.
A memory circuit comprising:
- a control circuit for reading and writing to individual memory cells;
- and
- a plurality of memory cells arranged in rows and columns to allow addressing of individual cells by the control circuit;
- each of said memory cells comprising an insulated gate field effect transistor with charge traps in an insulating layer, wherein substantially all of the charge traps are located within approximately 1.0 nm of an interface between a semiconductor layer and the insulating layer;
- and
- wherein, for each transistor, a gate is connected to a wordline, a source is connected to a first bit-line and a drain is connected to a second bit-line.
The memory circuit comprising:
- a control circuit for reading and writing to individual memory cells;
- and
- a plurality of memory cells arranged in rows and columns to allow addressing of individual cells by the control circuit, each of said memory cells comprising an insulated gate field effect transistor with charge traps in an insulating layer, said charge traps for retaining charge at or near an interface between a semiconductor layer and the insulating layer, said retained charge for modulating a threshold of the transistor;
- wherein substantially all of the change traps are located within approximately 1.0 nm of the interface;
- and
- wherein, for each transistor, a gate is connected to a wordline, a source is connected to a first bit-line and a drain is connected to a second bit-line.
Dependencies are inferred from the claim text.