Microelectronic device with centered storage capacitor cavity sized less than feature size

Abstract

A method of forming an integrated circuit capacitor is disclosed comprising the steps of providing a substrate, forming a conductive region at the substrate, and forming an insulating layer on the conductive region and the substrate. The method further comprises the steps of removing selective portions of the insulating layer to expose a selective area of the conductive region thereby forming a storage node contact window and forming a first conductive layer on the insulating layer and within the storage node contact window wherein the first conductive layer is in electrical communication with the conductive region. Next a cavity is formed in the first conductive layer. Subsequently, selected portions of the first conductive layer are removed leaving at least a remaining portion of the first conductive layer in which the cavity is formed thereby isolating the remaining portion of the first conductive layer from surrounding circuit elements. The capacitor is completed by forming a dielectric layer over the storage electrode and forming a second conductive layer over the dielectric layer to act as a plate electrode capacitively-coupled to the storage electrode through the dielectric layer. Other devices, systems and methods are also disclosed.

Dependencies are inferred from the claim text.