Flash EEprom system

A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising:

• providing said memory array and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system,
• partitioning the memory cells within the individual sectors into at least a user data portion and an overhead portion,
• causing the controller, in response to receipt from the processor of an address in a format designating at least one magnetic disk sector, to designate an address of at least one non-volatile memory sector that corresponds with said at least one magnetic disk sector,
• either writing user data to, or reading user data from, the user data portion of said at least one non-volatile memory sector, and
• either writing to, or reading from, said overhead portion of said at least one non-volatile memory sector, overhead data related either to said at least one non-volatile memory sector or to data stored in the user data portion of said at least one non-volatile memory sector.

A memory system on a card that is connectable to a host computer system, said memory system comprising:

• an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said memory cells that are erasable together as a unit, the individual sectors having enough cells for storing a given amount of user data and overhead data, and
• means connectable to said computer system for controlling operation of the array, said controlling means including:
• means responsive to receipt of a magnetic disk sector address from the host computer system for addressing a corresponding non-volatile memory sector,
• means for reading the overhead data stored in the addressed sector prior to either reading the user data from, or writing user data to, the addressed sector, and
• means responsive to the read overhead data for executing an instruction from the host computer system to perform a designated one of reading user data from, or writing user data to, the addressed sector.

A memory system having electrical terminations for establishing a connection with a host computer system, said memory system comprising:

• an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said memory cells that are erasable together as a unit, the individual sectors having enough cells for storing a given amount of user data and some overhead data, and
• a memory controller connected between said electrical terminations and said memory cell array for controlling operation of the array, said controller including:
• means responsive to receipt of one or more mass memory storage block addresses through said terminations for addressing one or more of the non-volatile memory sectors, said addressing means including means responsive to an identification of any of the non-volatile memory sectors that are unusable for substituting another usable sector therefor,
• means for reading overhead data stored in the addressed sector prior to either reading the user data from, or writing User data to, the addressed sector, and
• means responsive to the read overhead data for either reading user data from, or writing user data to, the addressed sector.

In a computer system including a processor and a memory system, wherein the memory system includes an array of integrated electronic circuit non-volatile floating gate memory cells partitioned into a plurality of distinct sectors of said memory cells that are individually erasable together as a unit separately from other sectors, a method of operating the memory system, comprising:

• removably connecting said memory system including a controller to the computer system in a manner that said controller communicates with said processor for controlling operation of the array,
• in response to receipt from the processor of an address in a format designating at least one mass memory storage block, generating through the controller (1) an address of at least one of said plurality of sectors of non-volatile memory corresponding to said at least one mass memory storage block and (2) an erase, write or read command,
• in response to an erase command, erasing said at least one sector,
• in response to a write command, reading, from an overhead portion of said at least one sector, overhead data of a characteristic of said at least one sector, and thereafter writing user data in the user data portion of said at least one sector and writing a characteristic of the written user data in the overhead portion of said at least one sector, and
• in response to a read command, reading, from an overhead portion of said at least one sector, overhead data of a characteristic of said at least one sector or of data stored in the user data portion of said at least one sector, and thereafter reading data from the user data portion of said at least one sector.