Integrated zener diode protection structures and fabrication methods for DMOS power devices

A method of fabricating an overvoltage protection device for an input of a semiconductor device, the method comprising the steps of:

• growing a gate oxide layer on an underlying epitaxial layer of a first conductivity type;
• forming a gate conductive layer on the gate oxide layer;
• defining a first field plate photolithographic mask over the gate conductive layer that protects a field plate region;
• etching the conductive layer through the first field plate photolithographic mask so as to form a field plate;
• implanting body impurities of a second conductivity type to form an input pad body implant region;
• removing the first field plate photolithographic mask;
• performing a thermal zener drive-in step to diffuse the body impurities of the second conductivity type vertically and laterally to form a diffused input pad body implant region;
• defining a first gate photolithographic mask over the gate conductive layer that protects a gate region;
• etching the conductive layer through the first gate photolithographic mask so as to form a gate;
• implanting body impurities of a second conductivity type to form a transistor body implant region;
• removing the first gate photolithographic mask;
• performing a thermal body drive-in step to diffuse the body impurities of the second conductivity type vertically and laterally to form a diffused transistor body region;
• defining a second photolithographic mask that exposes a heavy body contact region within the diffused transistor body region;
• implanting body contact impurities of the second conductivity type to form a heavy body implant region;
• removing the second photolithographic mask;
• performing a thermal body contact drive-in step to diffuse the body contact impurities of the second conductivity type vertically and laterally to form a diffused heavy body region;
• defining a third photolithographic mask that exposes a source region within the diffused transistor body region and a zener diode cathode region within the diffused input pad body region;
• implanting source impurities of the first conductivity type to form a source implant region and a zener cathode implant region;
• removing the third photolithographic mask;
• performing a thermal source drive-in step to diffuse the source impurities of the first conductivity type vertically and laterally to form a diffused source region and a diffused zener cathode region;
• depositing an insulation layer;
• defining a fourth photolithographic mask that protects the gate and portion of the field plate and exposes portions of the diffused source region and the diffused zener cathode region;
• etching the insulation layer through the fourth photolithographic mask;
• depositing a metal layer;
• defining a fifth photolithographic mask that protects an input pad metal region and a source metal region and exposes a region overlying the field plate;
• and
• etching the metal layer through the fifth photolithographic mask.