Distributed write data drivers for burst access memories

A memory device comprising:

• a plurality of write data drivers comprising an enable input, a data input and a data output;
• a plurality of data lines, each of said data lines coupled to the data output of at least one of said write data drivers;
• and
• a plurality of write data driver enable circuits, each of said write data driver enable circuits adapted to receive a write cycle control signal and an equilibrate control signal, each of said write data driver enable circuits located in close proximity and coupled to the enable input of at least one of said write data drivers.

A memory device comprising:

• a memory element array region;
• a plurality of data line pairs dispersed within said memory element array region;
• and
• a plurality of write data drivers dispersed along an edge of said memory element array region, each comprising an equilibrate input, a write active input, a write data input and a write data output, each of said write data drivers adapted to drive a data signal from the write data input to at least one of said data line pairs.

A memory device comprising:

• a memory element array region;
• a control circuit region, outside of said memory element array region, for generating memory control signals including an equilibrate signal and a write enable signal;
• a plurality of data line pairs dispersed throughout said memory element array region;
• a plurality of data sense amplifiers, said data sense amplifiers distributed along an edge of said memory element array region, each amplifier proximately located to at least one of said data line pairs;
• and
• a distributed plurality of write data drivers each comprising an equilibrate inactive input enable responsive to the equilibrate signal and a write active input enable responsive to the write enable signal, each of said write data drivers proximately located to a data sense amplifier and associated with at least one of said data line pairs.

A memory device comprising:

• a data input;
• a plurality of memory element subarrays;
• and
• a plurality of data sense amplifiers coupled to said subarrays, each of said data sense amplifiers comprising a write data driver responsive to an active write enable signal and an inactive equilibration signal, to drive write data received on said data input to a corresponding one of said subarrays.

A method of storing data in a system comprising steps of:

• providing a memory having a distributed plurality of data driver enable circuits;
• addressing the memory;
• providing data to the memory;
• asserting an equilibration signal at the plurality of data driver enable circuits in response to said step of addressing;
• asserting a write enable signal to the plurality of data driver enable circuits;
• deasserting the equilibration signal;
• gating a write enable signal through at least one of the data driver enable circuits in response to said step of deasserting;
• and
• storing data in a memory cell of the memory in response to said step of gating a write enable signal.