Analog-to-digital converter having reduced circuit area

An analog-to-digital converter comprising:

• a reference resistor array consisting of a plurality of resistor means connected in series arrangement and dividing the reference voltage across said plurality of resistor means connected in series arrangement into a plurality of reference potentials;
• an array of voltage dividing resistor means consisting of a plurality of resistor means connected in series arrangement and dividing the potential difference between an analog input signal supplied to one end of said series arrangement of said plurality of resistor means and a predetermined potential supplied to another end of said series arrangement of said plurality of resistor means into a plurality of divided analog signals attenuated by a voltage gradient which is different from the voltage gradient provided by said plurality of reference potentials;
• a plurality of differential amplification means for comparing said plurality of divided analog signals with said plurality of reference potentials corresponding to said divided analog signals, respectively, and outputting in-phase output signals and reversed-phase output signals;
• a plurality of first comparison means for comparing in-phase output signals with reversed-phase output signals corresponding to the mutually equivalent reference potentials with respect to said plurality of reference potentials and outputting the comparison output of said divided analog signals corresponding to the respective reference potentials;
• a plurality of second comparison means for comparing in-phase output signals with reversed-phase output signals corresponding to mutually differing potentials with respect to mutually adjacent potentials of said plurality of reference potentials and outputting the comparison output of said divided analog signals with regard to virtual reference potentials bisecting the space between the reference potentials;
• and
• an encoding means for converting said analog input signals into digital data of predetermined resolution on the basis of comparison output input from said first and said second comparison means;
• wherein the voltage gradient of said array of voltage dividing resistor means is half the voltage gradient of said plurality of reference potentials.

A serial-parallel type analog-to-digital converter, which converts analog input signals into digital data a plurality of times by a predetermined number of bits at a time, comprising:

• a reference resistor array consisting of a plurality of resistor means connected in series and dividing the reference voltage across said plurality of resistor means connected in series to a plurality of reference potentials;
• a voltage dividing resistor array consisting of a plurality of resistor means connected in series and dividing the potential difference between an analog input signal applied to one end of said plurality of resistor means connected in series and a predetermined potential supplied to the other end of said plurality of resistor means to a plurality of divided analog signals attenuated by a voltage gradient which is different from a voltage gradient of said plurality of reference potentials;
• a plurality of differential amplification means for comparing said plurality of divided analog signals with said plurality of reference potentials corresponding to said divided analog signals, respectively, and outputting in-phase output signals and reversed-phase output signals;
• a plurality of first comparison means for comparing in-phase output signals with reversed-phase output signals corresponding to the mutually equivalent reference potentials with respect to said plurality of reference-potentials and outputting the comparison output of said divided analog signals corresponding to the respective reference potentials;
• a plurality of second comparison means for comparing in-phase output signals with reversed-phase output signals corresponding to mutually differing potentials with respect to mutually adjacent potentials of said plurality of reference potentials and outputting the comparison output of said divided analog signals corresponding to the virtual reference potentials bisecting the space between the reference potentials;
• and
• an encoding means for converting said analog input signals into digital data of a predetermined resolution on the basis of comparison output input from said first and said second comparison means;
• wherein the voltage gradient of said plurality of divided analog signals is set at half the voltage gradient of said plurality of reference potentials.

An analog-to-digital converter comprising:

• a reference resistor array consisting of a plurality of resistor means connected in series and dividing the reference voltage across said plurality of resistor means connected in series into a plurality of reference potentials;
• an array of voltage dividing resistors consisting of a plurality of resistor means-connected in series and dividing the potential difference between an analog input signal supplied to one end of said plurality of resistor means connected in series, and a predetermined potential applied to another end by said plurality of resistor means into a plurality of divided analog signals attenuated by a voltage gradient which is different from voltage gradient of said plurality of reference potentials;
• a plurality of differential amplification means for comparing said plurality of analog signals with said plurality of reference potentials corresponding to said analog signals, respectively, and outputting in-phase output currents and reversed-phase output currents;
• a current dividing means for dividing in-phase output currents and reversed-phase output currents corresponding to said plurality of reference potentials as divided in-phase output currents and divided reversed-phase output currents, respectively;
• a current composition means for generating a composite in-phase output current by adding a plurality of divided in-phase output currents generated corresponding to mutually adjacent reference potentials at a predetermined proportion or generating a composite reversed-phase output current by adding a plurality of divided reversed-phase output currents generated corresponding to mutually differing reference potentials in a predetermined proportion;
• a plurality of first comparison means for comparing divided in-phase output currents with divided reversed-phase output currents corresponding to mutually equivalent reference potentials with respect to said plurality of reference potentials and outputting the comparison output of said divided analog signals corresponding to the respective reference potentials;
• a plurality of second comparison means for comparing divided in-phase output signals with divided reversed-phase output signals corresponding to mutually differing potentials with respect to mutually adjacent potentials of said plurality of reference potentials and outputting the comparison output of said divided analog signals corresponding to virtual reference potentials bisecting the space between the reference potentials;
• a plurality of third comparison means for comparing said plurality of composite in-phase output currents with said divided reversed-phase output current, respectively, or else said plurality of composite reversed-phase output currents with said plurality of divided in-phase output currents, and outputting the comparison output of said divided analog signals corresponding to virtual reference potentials multiply uniform between the reference potentials;
• and an encoding means for converting said analog input signals into digital data of predetermined resolution on the basis of comparison output input by said first, said second, or said third comparison means.

A serial-parallel type analog-to-digital converter, which converts analog input signals into digital data a plurality of times by a predetermined number of bits at a time, comprising:

• a reference resistor array consisting of a plurality of resistor means connected in series and dividing the reference voltage across said plurality of resistor means connected in series into a plurality of reference potentials;
• a voltage dividing resistor array consisting of a plurality of resistor means connected in series and dividing the potential difference between an analog input signal supplied to one end of said plurality of resistor means connected in series and a predetermined potential supplied to another end of said plurality of resistor means into a plurality of divided analog signals attenuated by a voltage gradient which is different from a voltage gradient of said plurality of reference potentials;
• a plurality of differential amplification means for comparing said plurality of divided analog signals with said plurality of reference potentials corresponding to said divided analog signals, respectively, and outputting in-phase output currents and reversed-phase output currents;
• a current dividing means for dividing in-phase output currents and reversed-phase output currents corresponding to said plurality of reference potentials as divided in-phase output currents and divided reversed-phase output currents, respectively;
• a current composition means for generating a composite in-phase output current by adding a plurality of divided in-phase output currents generated corresponding to mutually adjacent reference potentials in a predetermined proportion or generating a composite reversed-phase output current by adding a plurality of divided reversed-phase output currents generated corresponding to mutually differing reference potentials in a predetermined proportion;
• a plurality of first comparison means for comparing divided in-phase output currents with divided reversed-phase output currents corresponding to mutually equivalent reference potentials with respect to said plurality of reference potentials and outputting the comparison output of said divided analog signals corresponding to the respective reference potentials;
• a plurality of second comparison means for comparing divided in-phase output signals with divided reversed-phase output signals corresponding to mutually differing potentials with respect to mutually adjacent potentials of said plurality of reference potentials and outputting the comparative output of said divided analog signals corresponding to virtual reference potentials bisecting the space between reference potentials;
• a plurality of third comparison means for comparing said plurality of composite in-phase output currents with said divided reversed-phase output current, respectively, or else said plurality of composite reverse phase output currents with said plurality of divided in-phase output currents, respectively, and outputting the comparative output of said divided analog signals corresponding to virtual reference potentials multiply uniform between the reference potentials;
• and
• an encoding means for converting said analog input signals into digital data of a predetermined resolution on the basis of comparison output input by said first, said second, or said third comparison means.

A serial-parallel analog-to-digital converter circuit which converts analog signal into digital data by dividing said analog signal into two steps of high-order bits and low-order bits, wherein:

• a high-order comparator section obtains high-order bits by comparing said analog signal with a plurality of first reference voltage levels and obtains a pair of in-phase output signals and reversed-phase output signals by comparing the first reference voltage levels with said analog signal with respect to each of said first reference voltage levels, and after that,
• generates a plurality of in-phase shunt signals and reversed-phase shunt signals by dividing the in-phase output signal and reversed-phase output signal at a predetermined rate,
• generates an in-phase composite signal and a reversed-phase composite signal by adding in-phase shunt signals and reversed-phase shunt signals at a predetermined rate, which were generated with respect to reference voltage levels which are different from each other among the in-phase shunt signals and reversed-phase shunt signals,
• obtains a comparison output for a virtual reference voltage level which divides said first reference voltage levels at a predetermined rate by comparing said in-phase shunt signals with said reversed-phase composite signal or said reversed-phase shunt signals with said in-phase composite signal, and
• converts said analog signal into high-order bits by use of a comparison output for said virtual reference voltage levels in addition to said first reference voltage levels, and wherein
• a low-order comparator section which obtains low-order bits by comparing a plurality of second reference voltage levels, which are set based on the result of comparison of said high-order comparator section, with said analog signal converts said analog signal, which is divided with a voltage gradient different from the voltage gradient of said second reference voltage levels by means of a plurality of resistors which are connected in series, with said second reference voltage levels.

A serial-parallel analog-to-digital converter circuit which converts an analog signal into digital data by dividing said analog signal into two sets of high-order bits and low-order bits, wherein:

• a high-order comparator section which obtains high-order bits by comparing said analog signal with a plurality of first reference voltage levels, wherein said high-order comparator provides in-phase output signals and reversed-phase output signals by comparing the first reference voltage levels with said analog signal with respect to each of said first reference voltage levels, and after that,
• generates two sets of in-phase shunt signals and two sets of reversed-phase shunt signals by dividing the in-phase output signal and reversed-phase output signal at the ratio of 1 to 2,
• generates an in-phase composite signal and a reversed-phase composite signal by adding in-phase shunt signals and reversed-phase shunt signals at the ratio of 1 to 1, which were generated with respect to reference voltage levels which are different from each other among two sets of in-phase shunt signals and two sets of reversed-phase shunt signals,
• obtains comparison outputs for three sets of virtual reference voltage levels which divide said first reference voltage levels into four equal parts, respectively, by comparing said two sets of in-phase shunt signals with said reversed-phase composite signal or said two sets of reverse phase shunt signals with said in-phase composite signal, and
• converts said analog signal into high-order bits by use of comparison outputs for said three sets of virtual reference voltage levels in addition to said first reference voltage levels, and wherein a low-order comparator section which obtains low-order bits by comparing a plurality of second reference voltage levels, which are set based on the result of comparison of said high-order comparator section, with said analog signal converts said analog signal into low-order bits by comparing said analog signal, which is divided with a voltage gradient different from the voltage gradient of said second reference voltage levels by means of a plurality of resistors which are connected in series, with said second reference voltage levels.

A serial-parallel analog-to-digital converter circuit which converts analog signal into digital data by dividing conversion operation into two steps of high-order bits and low-order bits, wherein:

• a low-order comparator section which obtains low-order bits by comparing a plurality of first reference voltage levels obtained as a result of comparison of a high-order comparator section with said analog signal supplies said analog signal, which is divided with a voltage gradient different from the voltage gradient of said first reference voltage levels by means of a plurality of resistors which are connected in series,
• obtains a pair of in-phase output signal and reversed-phase output signal by comparing the first reference voltage levels with said analog signal which is divided by means of resistors with respect to each of said first reference voltage levels,
• obtains a comparison output responding to a virtual reference voltage level which divides said first reference voltage levels into two parts by comparing in-phase output signal with reversed-phase output signal obtained in correspondence with reference voltage levels which are different from each other, and
• converts said analog signal into low-order bits by use of a comparison output responding to said virtual reference voltage level in addition to said first reference voltage levels.

A serial-parallel analog-to-digital converter circuit which converts an analog signal into digital data by dividing said analog signal into two steps of high-order bits and low-order bits, wherein

• a low-order comparator sectional which obtains low-order bits by comparing a plurality of first reference voltage levels that result from a comparison of a high-order comparator section with said analog signal, supplies said analog signal, which is divided with a voltage gradient different from the voltage gradient of said first reference voltage levels, by means of a plurality of resistors which are connected in series,
• obtains a pair of in-phase output signal and reversed-phase output signal by comparing the first reference voltage levels with said analog signal, which is divided by means of resistors, with respect to each of said first reference voltage levels, and after that,
• generates a plurality of in-phase shunt signals and reversed-phase shunt signals by dividing the in-phase output signal and reversed-phase output signal at a predetermined rate,
• generates an in-phase composite signal and a reversed-phase composite signal by adding in-phase shunt signals and reversed-phase shunt signals at a predetermined rate, which were generated with respect to reference voltage levels which are different from each other among the in-phase shunt signals and reversed-phase shunt signals,
• obtains a comparison output responding to a virtual reference voltage level which divides said first reference voltage levels at a predetermined rate by comparing said in-phase shunt signals with said reversed-phase composite signal or said reversed-phase shunt signals with said in-phase composite signal, and
• converts said analog signal into low-order bits by use of a comparison output responding to said virtual reference voltage levels in addition to said first reference voltage levels.

A serial-parallel analog-to-digital converter circuit which converts an analog signal into digital data by dividing conversion operation into two steps of high-order bits and low-order bits, wherein:

• a low-order comparator section which obtains low-order bits by comparing a plurality of first reference voltage levels that result from a comparison of a high-order comparator section with said analog signal, supplies said analog signal, which is divided with a voltage gradient different from the voltage gradient of said first reference voltage levels, by means of a plurality of resistors which are connected in series,
• obtains a pair of in-phase output signal and reversed-phase output signal by comparing the first reference voltage levels with said analog signal, which is divided by means of resistors, with respect to each of said first reference voltage levels, and after that,
• generates two sets of in-phase shunt signals and two sets of reversed-phase shunt signals by dividing the in-phase output signal and reversed-phase output signal at the ratio of 1 to 2,
• generates an in-phase composite signal and a reversed-phase composite signal by adding in-phase shunt signals and reversed-phase shunt signals at the ratio of 1 to 1, which were generated with respect to reference voltage levels which are different from each other among two sets of in-phase shunt signals and two sets of reversed-phase shunt signals,
• obtains a comparison output corresponding to three sets of virtual reference voltage levels which divide said first reference voltage levels into four equal parts, respectively, by comparing said two sets of in-phase shunt signals with said reversed-phase composite signal or said two sets of reversed-phase shunt signals with said in-phase composite signal, and
• converts said analog signal into low-order bits by use of a comparison output corresponding to said three sets of virtual reference voltage levels in addition to said first reference voltage levels.